NM9805CV ETC [List of Unclassifed Manufacturers], NM9805CV Datasheet - Page 7

• Manufacturer Part Number: NM9805CV
• Description: PCI + 1284 Printer Port
• Manufacturer: ETC [List of Unclassifed Manufacturers]

PCI bus operation:
The execution of PCI bus transaction takes place in
broadly five stages: address phase; transaction claim-
ing; data phase(s); final data transfer; and transaction
completion.
Address phase:
Every PCI transaction starts off with an address phase,
one PCI clock period in duration. During address phase
the initiator (also known as current bus master) identi-
fies the target device (via the address) and type of trans-
action (via the command). The initiator drives the 32-bit
address onto 32-bit address/data bus and 4-bit com-
mand onto 4-bit command/byte enable bus. The initia-
tor also asserts the nFRAME signal during the same
clock cycle to indicate the presence of valid address
and transaction type on those buses. The initiator sup-
plies start address and command type for one PCI clock
cycle. The target, Nm9805, generates the subsequent
sequential addresses for burst transfers. The address/
data bus becomes data bus and command/byte enable
bus becomes byte enable bus for the remainder of the
clock cycles of that transaction. The target (Nm9805)
latches the address and command type on the next ris-
ing edge of PCI clock, as do all the devices on that PCI
bus. The target (Nm9805) decodes the address and
determines whether it is being addressed, and decodes
the command to determine the type of transaction.
Claiming the transaction:
When Nm9805 determines that it is the target of a trans-
action, it claims the transaction by asserting nDEVSEL.
Data phase(s):
The data phase of a transaction is the period during
which a data object is transferred between the initiator
and the target (Nm9805). The number of data bytes to
be transferred during a data phase is determined by
the number of command/byte enable signals that are
asserted by the initiator during the data phase. Each
data phase is at least one PCI clock period in duration.
Both initiator and target must indicate that they are ready
to complete a data phase. If not, the data phase is ex-
tended by a wait state of one clock period in duration.
The initiator and the target indicate this by asserting
nIRDY and nTRDY respectively and the data transfer is
completed at the rising edge of the next PCI clock.
Rev. 1.1
Transaction duration:
The initiator, as stated earlier, gives only start address
during address phase but does not tell the number of
data transfers in a burst transfer transaction. However,
the initiator indicates the completion of data transfer of
a transaction by asserting nIRDY and de-asserting
nFRAME during the last data transfer phase. The trans-
action, however, does not complete until the target has
also asserted the nTRDY signal and the last data trans-
fer takes place. At this point the nTRDY and nDEVSEL
are de-asserted by the target.
Transaction completion:
When all of nIRDY, nTRDY, nDEVSEL, and nFRAME
are in inactive state (high state), the bus is in idle state.
The bus is ready to be claimed by another bus master.
Internal address select configuration
I/O Address Function
YX0-YX07
WX00
WX01
WX02
PCI + 1284 Printer Port
Standard Printer
Printer Configuration Register A
Printer Configuration Register B
Printer ECR Register
Nm9805
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