NM9805CV ETC [List of Unclassifed Manufacturers], NM9805CV Datasheet - Page 12

• Manufacturer Part Number: NM9805CV
• Description: PCI + 1284 Printer Port
• Manufacturer: ETC [List of Unclassifed Manufacturers]

Nm9805
PCI + 1284 Printer Port
Mode “010”
FIFO Output Mode
In this mode, bytes written to the FIFO are transmitted
automatically using the SPP/Centronics standard pro-
tocol.
Mode “011”
Extended Capability Port “ECP” Mode
The ECP provides an advanced mode for communica-
tion with printer or peripherals. Like EPP protocol, ECP
provides 16-byte FIFO for a high performance bi-direc-
tional communication path between the host adapter
and the peripheral. The ECP protocol provides the fol-
lowing cycle types in both the forward and reverse di-
rections:
The RLE feature enables real time data compression
that can achieve compression ratios up to 64:1. This is
particularly useful for printers and peripherals that are
transferring large raster images that have large strings
of identical data. In order for the RLE mode to be en-
abled, both the host and peripheral must support it.
Channel addressing is intended to address multiple logi-
cal devices within a single physical device, like modem/
FAX/printer in one physical package.
Mode “100”
Enhanced Parallel Port “EPP” Mode
In EPP mode, nSLCTIN (address strobe) and nAUTOFD
(data strobe) are automatically generated while
nSTROBE indicates a write or read cycle. Additional I/
O addresses are defined for data and address access
and when these locations are used, handshaking is
performed automatically by Nm9805.
Mode “110”
FIFO Test Mode
In this mode, the FIFO can be written and read in any
direction, but no data will be transmitted on the PD7-
PD0 ports. Whatever data is in the FIFO may be dis-
played on the PD7-PD0 ports.
Page 12
Data cycle
Command cycles
Run-Length counts (RLE)
Channel address
ECR Bit-4:
Error Interrupt Enable.
0 = Enable nFAULT interrupt. nFAULT pin is used as
source of interrupt.
1 = Disable nFAULT interrupt (nACK is used as source
of interrupt).
ECR Bit-3:
0 = normal operating mode.
ECR Bit-2:
1 = Disables service interrupt.
0 = Enables one of the following 3 cases of interrupts.
One of the 3 service interrupts has occurred. Service
interrupt bit will be set to a “1” by hardware. Writing this
bit to a “1” will not cause an interrupt.
Port Direction (DCR Bit-5 = 0). This bit will be set to “1”
whenever there are write interrupt thresholds (4 char-
acters) or more bytes free in the FIFO. The Nm9805
generates interrupt when this condition is occurred and
service interrupt is cleared to “0”.
Port Direction (DCR Bit-5 = 1). This bit will be set to “1”
whenever there are read interrupt thresholds (12 char-
acters) or more bytes to be read from the FIFO. The
Nm9805 generates interrupt when this condition is oc-
curred and service interrupt is cleared to “0”.
ECR Bit-1:
0 = One or more empty locations in FIFO is available.
1 = FIFO full.
ECR Bit-0:
0 = One or more data in FIFO.
1 = FIFO empty.
Rev. 1.1