ZR36057 ZORAN [Zoran Corporation], ZR36057 Datasheet - Page 33

• Manufacturer Part Number: ZR36057
• Description: ENHANCED PCI BUS MULTIMEDIA CONTROLLER
• Manufacturer: ZORAN [Zoran Corporation]

12.20 JPEG Mode and Control
This register contains the JPEG Mode configuration and optional
control bits.
Address Offset: 0x100
30 : 29
28 : 7
Bit
31
6
5
4
Type
RW
RW
RW
RW
RW
R
Mod
jpg
jpg
jpg
all
JPG- JPEG/MPEG mode selection. This bit
selects between the two code DMA controller
modes.
‘1’ - JPEG Mode.
‘0’ - MPEG Mode.
Default value is ‘0‘
JPGMode - JPEG Sub-Modes Selection.
These two bits configure the JPEG sub-
mode.
11b - Motion Video Compression.
10b - Motion Video Decompression.
01b - Still Image Compression.
00b - Still Image Decompression.
Default value is 11b
Reserved. Returns zero.
RTBSY_FB - RTBSY Feed-Back. This
control bit enables the ZR36057 to de-assert
dynamically (during a process) the PXEN
signal if RTBSY is detected in the active area
of the field.
‘1’ - Enable PXEN de-assertion if RTBSY is
detected.
‘0’ - Disable PXEN de-assertion.
Default value is ‘0’
Go_en - The enable bit of the ZR36050 GO
command cycle. The bit, when ‘1’, enables
the GuestBus Master to perform a JPEG GO
cycle. During the JPEG GO cycle the
ZR36057 assumes that the correct address
(0x00h) is pre-latched in an external address
register. It is the host’s responsibility to
perform the write operation to load the
address. The host must de-assert Go_en
whenever it accesses the ZR36050 (using
PostOffice) in a middle of a JPEG process, or
changes the address latched in the external
register. The host must also de-assert Go_en
before PostOffice pseudo write-through burst
cycles. In this case, the host also has to wait
at least 0.5 microseconds before initiating the
burst (to allow the JPEG GO cycle to com-
plete, if one was started).
Default value is ‘0’ (Go not enabled).
SyncMstr - Sync Signals Master. This bit
configures the ZR36057 as a sync master.
This configuration is allowed in all JPEG
modes except Motion Video Compression
‘1’ - The ZR36057 is the sync signal master.
‘0’ - The sync signals are driven from an
external video source.
Default value is ‘0’
Description
Enhanced PCI Bus Multimedia Controller
33
Address Offset: 0x100 (Continued)
12.21 JPEG Process Control
This register contains the JPEG process control.
Address Offset: 0x104
31: 8
Bit
Bit
3
2
1
0
7
6
5
Type
Type
RW
RW
RW
RW
RW
RW
R
R
Mod
Mod
jpg
jpg
jpg
jpg
all
Fld_per_buff - Number of Fields Per Code
Buffer. This bit reflects the system memory
code buffer structure in JPEG Compression
and Decompression modes.
‘1’ - The code buffer contains one code field.
‘0’ - The code buffer contains two consecutive
code fields, one code frame.
Default value is ‘0‘
VFIFO_FB - VFIFO Feed-Back. This control
bit enables the ZR36057 to de-assert dynam-
ically (during a process) the PXEN signal
according to the status of the Video FIFO.
‘1’ - Enable PXEN de-assertion if the pixel
buffer is close to overflow.
‘0’ - Disable PXEN de-assertion if the pixel
buffer is close to overflow.
Default value is ‘0’
CFIFO_FB - CFIFO Feed-Back. This control
bit enables the ZR36057 to de-assert dynam-
ically (during a process) the PXEN signal
according to the status of the Code FIFO.
‘1’ - Enable PXEN de-assertion if the code
buffer is close to overflow/underflow.
‘0’ - Disable PXEN de-assertion if the code
buffer is close to overflow/underflow.
Default value is ‘0’
Still_LitEndian - Still image pixel Little
Endian format selector. This control bit
defines the pixel format in Still Image Com-
pression and Decompression.
‘1’ - The pixel format is Little Endian.
‘0’ - The pixel format is Gib Endian.
Default value is ‘1’.
Reserved. Returns zero.
P_reset - Process Reset. This bit is asserted
by the host in order to reset the ZR36057
JPEG-related state machines. The bit must
be asserted at the beginning of a JPEG
process. While it is asserted, all of the JPEG
process parameters may be configured by
the host.
‘1’ - No reset.
‘0’ - Reset.
Default value is ‘1’.
Reserved, Returns zero.
CodTrnsEn - JPEG Code Transfer Enable.
This bit enables the code transfer between
the internal code buffer and the system
memory in all of the JPEG modes.
‘1’ - Code transfer is enabled.
‘0’ - code transfer is disabled.
Default value is ‘0’.
Description
Description