ZR36057 ZORAN [Zoran Corporation], ZR36057 Datasheet - Page 22

• Manufacturer Part Number: ZR36057
• Description: ENHANCED PCI BUS MULTIMEDIA CONTROLLER
• Manufacturer: ZORAN [Zoran Corporation]

Enhanced PCI Bus Multimedia Controller
In Motion Video Decompression mode, if the ZR36057 starts a
new fragment when the Code FIFO is exactly full, the Code FIFO
can sometimes overflow.
There are two possible ways to deal with this problem:
• If a new code buffer is unavailable at the beginning of a field
• When the host receives the interrupt, it checks the
declaring that this buffer was already decompressed, issues
an interrupt, and starts the next field/frame process. It reads
the next STAT_COM entry from the code buffer table. If the
buffer is available, that is, the STAT_BIT=‘0‘ indicating it
contains the code of a new field/frame, the ZR36057 starts
transferring its fragments for decompression.
or frame process (that is, if the STATUS_BIT of the next
buffer entry is ‘1’), the ZR36057 repeats decompression of
the last available code buffer.
STAT_COM entries in the code buffer table. For each entry
whose STAT_BIT=’1’, the host loads compressed data into
a new code buffer and updates its fragment table, then re-
turns the buffer by resetting its STAT_BIT to ‘0’.
Important Note:
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1. Copying the fragmented buffer into a single-fragment buffer
before playing it back.
Implementing this alternative may cause some performance
degradation due to the additional memory-to-memory copying.
2. Configuring the Code FIFO threshold to be low enough.
If the Code FIFO threshold is low enough, the Code FIFO will
never reach fullness. The maximum length of a single PCI burst
is limited, and after the Code FIFO gets above its threshold, the
PCI bus is not requested again.
The recommended parameters of the ZR36057 for this work-
around option are:
• The Triton bit (in the Video Display Configuration Register)
• Master Latency Timer = 48 (in the PCI Configuration Space
• JPEGCodTrshold (in the JPEG Code FIFO Threshold Reg-
should be 0. This bit causes the ZR36057’s REQ signal to
be de-asserted immediately after the bus was granted. Typi-
cally (on machines with Triton PCI chip set), this causes the
GNT signal to be de-asserted. The ZR36057’s burst length
is then determined by the Latency Timer parameter.
Register.
ister = 20.