AS4LC4M16DG-5S/IT AUSTIN [Austin Semiconductor], AS4LC4M16DG-5S/IT Datasheet - Page 4

• Manufacturer Part Number: AS4LC4M16DG-5S/IT
• Description: 4 MEG x 16 DRAM
• Manufacturer: AUSTIN [Austin Semiconductor]

DRAM ACCESS (continued)
LOW on WE\ dictates write mode. During a WRITE cycle,
data-in (D) is latched by the falling edge of WE or CAS\ (CASL\
or CASH\), whichever occurs last. An EARLY WRITE occurs
when WE is taken LOW prior to either CAS\ falling. A LATE
WRITE or READ-MODIFY-WRITE occurs when WE falls after
CAS\ (CASL\ or CASH\) is taken LOW. During EARLY WRITE
cycles, the data outputs (Q) will remain High-Z, regardless of
the state of OE\. During LATE WRITE or READ-MODIFY-
WRITE cycles, OE\ must be taken HIGH to disable the data
outputs prior to applying input data. If a LATE WRITE or
READ-MODIFY-WRITE is attempted while keeping OE\ LOW,
no write will occur, and the data outputs will drive read data
from the accessed location.
must be satisfied prior to changing modes of operation be-
tween the upper and lower bytes. For example, an EARLY
WRITE on one byte and a LATE WRITE on the other byte are
AS4LC4M16
Rev. 1.0 7/02
A logic HIGH on WE\ dictates read mode, while a logic
Additionally, both bytes are active. A CAS\ precharge
FIGURE 2: WORD and BYTE READ Example
Austin Semiconductor, Inc.
4
not allowed during the same cycle. However, an EARLY WRITE
on one byte and a LATE WRITE on the other byte, after a CAS\
precharge has been satisfied, are permissible.
EDO PAGE MODE
buffers off (High-Z) with the rising edge of CAS\. If CAS\ went
HIGH and OE\ was LOW (active), the output buffers would be
disabled. The 64MB EDO DRAM offers an accelerated page
mode cycle by eliminating output disable from CAS\ HIGH.
This option is called EDO, and it allows CAS\ precharge time
(t
and EDO-PAGE-MODE READ waveforms).
MODE READ, except data is held valid after CAS\ goes HIGH,
as long as RAS\ and OE\ are held LOW and WE\ is held HIGH.
OE\ can be brought LOW or HIGH while CAS\ and RAS\ are
LOW, and the DQs will transition between valid data and High-
Z. Using OE\, there are two methods to disable the outputs and
CP
) to occur without the output data going invalid (see READ
DRAM READ cycles have traditionally turned the output
EDO operates like any DRAM READ or FAST-PAGE-
Austin Semiconductor, Inc. reserves the right to change products or specifications without notice.
AS4LC4M16
DRAM
DRAM
DRAM
DRAM
DRAM