HY5PS1G831LF-C4 HYNIX [Hynix Semiconductor], HY5PS1G831LF-C4 Datasheet - Page 21

• Manufacturer Part Number: HY5PS1G831LF-C4
• Description: 1Gb DDR2 SDRAM
• Manufacturer: HYNIX [Hynix Semiconductor]

Rev. 1.2 / Dec 2006
* : tRAS(min) , tRC(min) specification for DDR2-400 4-4-4 is 45ns, 60ns respectively.
DQ output access time from CK/CK
DQS output access time from CK/CK
CK high-level width
CK low-level width
CK half period
Clock cycle time, CL=x
DQ and DM input setup time
DQ and DM input hold time
Control & Address input pulse width for each input
DQ and DM input pulse width for each input
Data-out high-impedance time from CK/CK
DQS low-impedance time from CK/CK
DQ low-impedance time from CK/CK
DQS-DQ skew for DQS and associated DQ signals
DQ hold skew factor
DQ/DQS output hold time from DQS
Write command to first DQS latching transition
DQS input high pulse width
DQS input low pulse width
DQS falling edge to CK setup time
DQS falling edge hold time from CK
Mode register set command cycle time
Write postamble
Write preamble
Address and control input setup time
Address and control input hold time
Read preamble
Read postamble
Activate to precharge command
Active to active command period for 1KB page size products
Active to active command period for 2KB page size products
Four Active Window for 1KB page size products
Parameter
tAC
tDQSCK
tCH
tCL
tHP
tCK
tDS
tDH
tIPW
tDIPW
tHZ
tLZ
(DQS)
tLZ
(DQ)
tDQSQ
tQHS
tQH
tDQSS
tDQSH
tDQSL
tDSS
tDSH
tMRD
tWPST
tWPRE
tIS
tIH
tRPRE
tRPST
tRAS
tRRD
tRRD
tFAW
Symbol
tHP - tQHS
WL - 0.25
2*tAC min
min(tCL,
tAC min
3000
-450
-400
0.45
0.45
tCH)
0.35
0.35
0.35
37.5
min
175
0.35
150
275
0.6
0.2
0.2
0.4
0.9
0.4
7.5
50
45
10
2
-
-
-
DDR2-667
WL + 0.25
tAC max
tAC max
tAC max
70000
+450
+400
max
0.55
0.55
8000
1HY5PS1G431(L)F
1HY5PS1G831(L)F
240
340
0.6
1.1
0.6
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Unit
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
tCK
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ps
ns
ns
ns
ns
6,7,8,20
6,7,8,21
5,7,9,22
5,7,9,23
11,12
Note
15
18
18
18
13
12
10
19
19
3
4
4
21