CH7006C-V ETC, CH7006C-V Datasheet - Page 42

• Manufacturer Part Number: CH7006C-V
• Description: Digital PC to TV Encoder Features
• Manufacturer: ETC

Register Descriptions (continued)
When this pin is selected to be an output, the buffered clock output register determines which clock is selected to be
output at the DS/BCO clock output pin and what frequency value is output when a VCO derived signal is output.The
tables below show the possible outputs.
Subcarrier Value Registers
The lower four bits of registers 18H through 1FH contain a 32-bit value which is used as an increment value for the
ROM address generation circuitry. The bit locations are specified as the following:
Register
18H
19H
1AH
1BH
1CH
1DH
1EH
1FH
Table 25. Clock Output Selection
Table 26. K3 Selection
CHRONTEL
42
SCO[2:0]
000
001
010
011
100
101
110
111
Bit:
Symbol:
Type:
Default:
SHF[2:0]
000
010
011
100
101
110
111
7
Contents
FSCI[31:28]
FSCI[27:24]
FSCI[23:20]
FSCI[19:16]
FSCI[15:12]
FSCI[11:8]
FSCI[7:4]
FSCI[3:0]
Buffered Clock Output
(for test use only)
VCO divided by K3 (see Table 26)
Field ID signal
Sine ROM MSB (for test use only)
(for test use only)
(for test use only)
TV vertical sync (for test use only)
14MHz crystal
K3
2.5
3.5
4.5
4
5
6
7
6
5
4
3
FSCI#
R/W
2
FSCI#
R/W
201-0000-026 Rev 2.1, 8/2/99
Symbol: FSCI
Address: 18H - 1FH
Bits: 4 or 8 each
1
FSCI#
R/W
CH7006C
0
FSCI#
R/W