CH7006C-V ETC, CH7006C-V Datasheet - Page 32

• Manufacturer Part Number: CH7006C-V
• Description: Digital PC to TV Encoder Features
• Manufacturer: ETC

Register Descriptions (continued)
Flicker Filter Register
The flicker filter register provides for adjusting the operation of the various filters used in rendering the on-screen
image. Adjusting settings between minimal and maximal values enables optimization between sharpness and
flicker content. The FC[1:0] bits determine the settings for the chroma channel. The FT[1:0] bits determine the
settings for the text enhancement circuit.
addition, the Chroma channel filtering includes a setting to enable the chroma dot crawl reduction circuit.
Note: When writing to register O1H, FY[1.0] is bits 3:2. FT[1:0] is bits 1:0. When reading from the register O1H, FY
CHRONTEL
32
Table 17. Flicker Filter Settings
VOS[1:0]
Output Format
Bit:
Symbol:
Type:
Default:
FY[1:0]
00
01
10
11
FT[1:0]
00
01
10
11
FC[1:0]
00
01
10
11
[1:0] is bits 1:0 and FT[1:0] is bits 3:2.
7
00
PAL
Settings for Luma Channel
Minimal Flicker Filtering
Slight Flicker Filtering
Maximum Flicker Filtering
Invalid
Settings for Text Enhancement Circuit
Maximum Text Enhancement
Slight Text Enhancement
Minimum Text Enhancement
Invalid
Settings for Chroma Channel
Minimal Flicker Filtering
Slight Flicker Filtering
Maximum Flicker Filtering
Enable Chroma DotCrawl Reduction
6
5
FC1
R/W
1
The FY[1:0] bits determine the settings for the luma channel.
01
NTSC
4
FC0
R/W
1
3
FY1
R/W
0
10
PAL-M
2
FY0
R/W
0
201-0000-026 Rev 2.1, 8/2/99
Symbol: FFR
Address: 01H
Bits: 6
1
FT1
R/W
1
11
NTSC-J
CH7006C
0
FT0
R/W
0
In