FX629J CMLMICRO [CML Microcircuits], FX629J Datasheet - Page 4

• Manufacturer Part Number: FX629J
• Description: Delta Modulation Codec
• Manufacturer: CMLMICRO [CML Microcircuits]

Codec Integration
Component
Fig.2 System Configuration Diagram – showing the FX629, which with the indicated interfacing, will conform to
the Mil-Std-188-113 Specification
Fig.3 Recommended External Components
Tolerance :– Resistors
R
R
C
C
C
C
C
X
1
2
1
2
3
4
5
1
SYSTEM
INPUT
C
2
C
1
C
ANALOGUE
INTERFACE
Unit Value
Selectable
4
1.024 MHz
X
BUFFER)
(BALUN
INPUT
1
1.0
1.0
1.0
R
33p
33p
1M
&
2
ENCODER DATA CLOCK
ENCODER FORCE IDLE
FX629 PARAMETERS
MEASURED HERE
ENCODER OUTPUT
10% Capacitors
C
ENCODER INPUT
3
DATA ENABLE
R
1
XTAL/CLOCK
Note –
Oscillator Inverter bias resistor.
Xtal Drive limiting resistor.
Xtal Circuit drain capacitor.
Xtal Circuit gate capacitor.
Encoder Input coupling capacitor – The drive source impedance to this
input should be less than 100 . Output Idle channel noise levels will
improve with an even lower source impedance.
Bias decoupling capacitor.
V
A 1.024 MHz Xtal/clock input will yield exactly 16/32/64 kb/s data clock
rates. Xtal circuitry shown is in accordance with CML application note
D/XT/1 April 1986.
1.024 MHz
XTAL
BIAS
DD
N/C
V
N/C
SS
ENCODER
decoupling capacitor.
FX629
DATA
with reference to Figure 3 (below)
CLOCKS
SYNCHRONOUS CLOCK
1
2
3
4
5
6
7
8
9
10
11
REGULATED POWER
20%
DATA SYSTEM
FX629J
CLOCK MODE
16/32/64kb/s
SUPPLY
AND
V
V
DD
SS
4
DATA
DECODER
22
21
20
19
18
17
16
15
14
13
12
FX629
CLOCKS
1.024 MHz
FX629 PARAMETERS
CLOCK MODE 1
CLOCK MODE 2
ALGORITHM
DECODER DATA CLOCK
DECODER INPUT
DECODER FORCE IDLE
POWERSAVE
N/C
DECODER OUTPUT
N/C
MEASURED HERE
V
DD
ANALOGUE
INTERFACE
BUFFER)
OUTPUT
(BALUN
&
SYSTEM
OUTPUT
C
5