EM78159NAS EMC [ELAN Microelectronics Corp], EM78159NAS Datasheet - Page 24

• Manufacturer Part Number: EM78159NAS
• Description: 8-Bit Microcontroller with OTP ROM
• Manufacturer: EMC [ELAN Microelectronics Corp]

EM78P159N
8-Bit Microcontrollerwith OTP ROM
20 •
The Sleep (power down) mode is asserted by executing the “SLEP” instruction. While
entering Sleep mode, WDT (if enabled) is cleared but keeps on running. The controller
can be awakened by-
1) External reset input on /RESET pin,
2) WDT time-out (if enabled), or
3) Port 6 input status change (if enabled).
The first two cases will cause the EM78P159N to reset. The T and P flags of R3 are
used to determine the source of the reset (wake-up). The last case is considered the
continuation of program execution and the global interrupt ("ENI" or "DISI" being
executed) decides whether or not the controller branches to the interrupt vector
following wake-up. If ENI is executed before SLEP, the instruction will begin to execute
from the address 008H after wake-up. If DISI is executed before SLEP, the operation
will restart from the succeeding instruction right next to SLEP after wake-up.
Wake-up time is dependent on oscillator mode. Under RC mode, the reset time is 32
clocks, and in High XTAL mode, reset time is 2ms and 32clocks. In Low XTAL mode,
the reset time is 500ms. The above is applicable only for stable oscillator.
Only one of Cases 2 and 3 can be enabled before going into the Sleep mode. That is,
[a] if Port 6 Input Status Change Interrupt is enabled before SLEP, WDT must be
[b] if WDT is enabled before SLEP, Port 6 Input Status Change Interrupt must be
disabled by software. However, the WDT bit in the option register remains enabled.
Hence, the EM78P159N can be awakened only by Case 1 or 3.
disabled. Hence, the EM78P159N can be awakened only by Case 1 or 2. Refer to
the Section 4.6, Interrupt for further details.
The Watchdog timer and prescaler are cleared.
When power is switched on, the upper 3 bits of R3 are cleared.
The bits of the CONT register are set to all "1" except for the Bit 6 (INT flag).
The bits of the IOCA register are set to all "1."
The bits of the IOCB register are set to all "1."
The IOCC register is cleared.
The bits of the IOCD register are set to all "1."
Bit 7 of the IOCE register is set to "1," and Bits 4 and 6 are cleared.
Bits 0 ~ 2 of RF and Bits 0 ~ 2 of IOCF registers are cleared.
(This specification is subject to change without further notice)
Product Specification (V1.0) 03.10.2006