K9K1G08U0B Samsung semiconductor, K9K1G08U0B Datasheet - Page 30

• Manufacturer Part Number: K9K1G08U0B
• Description: 128M x 8 Bit NAND Flash Memory
• Manufacturer: Samsung semiconductor

Figure 10. Program & Read Status Operation
PAGE PROGRAM
The device is programmed basically on a page basis, but it does allow multiple partial page programing of a byte or consecutive bytes
up to 528, in a single page program cycle. The number of consecutive partial page programming operation within the same page with-
out an intervening erase operation must not exceed 1 for main array and 2 for spare array. The addressing may be done in any ran-
dom order in a block. A page program cycle consists of a serial data loading period in which up to 528 bytes of data may be loaded
into the page register, followed by a non-volatile programming period where the loaded data is programmed into the appropriate cell.
Serial data loading can be started from 2nd half array by moving pointer. About the pointer operation, please refer to the attached
technical notes.
The serial data loading period begins by inputting the Serial Data Input command(80h), followed by the four cycle address input and
then serial data loading. The bytes other than those to be programmed do not need to be loaded.The Page Program confirm com-
mand(10h) initiates the programming process. Writing 10h alone without previously entering the serial data will not initiate the pro-
gramming process. The internal write state control automatically executes the algorithms and timings necessary for program and
verify, thereby freeing the system controller for other tasks. Once the program process starts, the Read Status Register command
may be entered, with RE and CE low, to read the status register. The system controller can detect the completion of a program cycle
by monitoring the R/B output, or the Status bit(I/O 6) of the Status Register. Only the Read Status command and Reset command are
valid while programming is in progress. When the Page Program is complete, the Write Status Bit(I/O 0) may be checked(Figure 10).
The internal write verify detects only errors for "1"s that are not successfully programmed to "0"s. The command register remains in
Read Status command mode until another valid command is written to the command register.
BLOCK ERASE
The Erase operation is done on a block(16K Byte) basis. Block address loading is accomplished in three cycles initiated by an Erase
Setup command(60h). Only address A
block address loading initiates the internal erasing process. This two-step sequence of setup followed by execution command
ensures that memory contents are not accidentally erased due to external noise conditions.
At the rising edge of WE after the erase confirm command input, the internal write controller handles erase and erase-verify. When
the erase operation is completed, the Write Status Bit(I/O 0) may be checked. Figure 11 details the sequence.
Figure 11. Block Erase Operation
K9K1G08R0B
K9K1G08B0B
K9K1G08U0B
R/B
I/O
R/B
I/O
0
0
~
~
7
7
60h
80h
A
Block Add. : A
Address Input(3Cycle)
Address & Data Input
0
528 Byte Data
~ A
7
& A
9
14
~ A
14
to A
26
~ A
26
26
is valid while A
10h
D0h
9
to A
30
13
t
t
BERS
PROG
is ignored. The Erase Confirm command(D0h) following the
70h
70h
FLASH MEMORY
I/O
Fail
I/O
Fail
0
Advance
0
Pass
Pass