M38197 Mitsubishi, M38197 Datasheet - Page 16

• Manufacturer Part Number: M38197
• Description: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
• Manufacturer: Mitsubishi

INTERRUPTS
Interrupts occur by 20 sources: 5 external, 14 internal, and 1 soft-
ware.
Interrupt Control
Each interrupt is controlled by an interrupt request bit, an interrupt
enable bit, and the interrupt disable flag except for the software in-
terrupt set by the BRK instruction. An interrupt occurs if the
corresponding interrupt request and enable bits are “1” and the in-
terrupt disable flag is “0”.
Interrupt enable bits can be set or cleared by software.
Interrupt request bits can be cleared by software, but cannot be
set by software.
The BRK instruction cannot be disabled with any flag or bit.
The I (interrupt disable) flag disables all interrupts except the BRK
instruction interrupt.
Table 1. Interrupt vector addresses and priority
Notes 1 : Vector addresses contain interrupt jump destination addresses.
16
Reset (Note 2)
INT
INT
INT
Remote control/
counter overflow
Serial I/O1
Serial I/O
automatic transfer
Serial I/O2
Serial I/O3
Timer 1
Timer 2
Timer 3
Timer 4
Timer 5
Timer 6
INT
INT
A-D conversion
FLD blanking
FLD digit
BRK instruction
Interrupt Source
0
1
2
3
4
/ZCR
2 : Reset function in the same way as an interrupt with the highest priority.
Priority
10
11
12
13
14
15
16
17
4
1
5
6
7
8
9
2
3
Vector Addresses (Note 1)
FFFD
FFED
FFEB
FFDF
FFDD
FFFB
FFF7
FFEF
FFE9
FFE7
FFE5
FFE3
FFE1
FFF9
FFF5
FFF3
FFF1
High
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
FFFC
FFDC
FFEE
FFEC
FFEA
FFDE
FFFA
FFF8
FFF6
FFF4
FFF2
FFF0
FFE8
FFE6
FFE4
FFE2
FFE0
Low
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
16
Interrupt Operation
When an interrupt is received, the contents of the program counter
and processor status register are automatically stored into the
stack. The interrupt disable flag is set to inhibit other interrupts
from interfering. The corresponding interrupt request bit is cleared
and the interrupt jump destination address is read from the vector
table into the program counter.
Notes on Use
When the active edge of an external interrupt (INT
changed or when switching interrupt sources in the same vector
address, the corresponding interrupt request bit may also be set.
Therefore, please take following sequence;
(1) Disable the external interrupt which is selected.
(2) Change the active edge.
(3) Clear the interrupt request bit which is selected to “0”.
(4) Enable the external interrupt which is selected.
At reset
At detection of either rising or
falling edge of INT
At detection of either rising or
falling edge of INT
At detection of either rising or
falling edge of INT
At 8-bit counter overflow
At completion of data transfer
At completion of the last data
transfer
At completion of data transfer
At completion of data transfer
At timer 1 underflow
At timer 2 underflow
At timer 3 underflow
At timer 4 underflow
At timer 5 underflow
At timer 6 underflow
At detection of either rising or
falling edge of INT
At detection of either rising or
falling edge of INT
At completion of A-D conver-
sion
At falling edge of the last digit
immediately before blanking
period starts
At rising edge of each digit
At BRK instruction execution
Generating Conditions
Interrupt Request
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
1
0
2
3
4
/ZCR input
input
input
input
input
MITSUBISHI MICROCOMPUTERS
Non-maskable
External interrupt (active edge
selectable)
External interrupt (active edge
selectable)
External interrupt (active edge
selectable)
Valid when interrupt interval
determination is operating
Valid when serial I/O ordinary
mode is selected
Valid when serial I/O automatic
transfer mode is selected
Valid when serial I/O2 is se-
lected
Valid when serial I/O3 is se-
lected
STP release timer underflow
External interrupt (active edge
selectable)
Valid when A-D conversion in-
terrupt is selected
Valid when FLD digit interrupt
is selected
Non-maskable software inter-
rupt
Valid when INT
selected
External interrupt (active
edge selectable)
Valid when FLD blanking in-
terrupt is selected
3819 Group
Remarks
4
interrupt is
0
to INT
4
) is