HM1-65262-9 INTERSIL [Intersil Corporation], HM1-65262-9 Datasheet - Page 6

• Manufacturer Part Number: HM1-65262-9
• Description: 16K x 1 Asynchronous CMOS Static RAM
• Manufacturer: INTERSIL [Intersil Corporation]

Timing Waveforms
NOTE:
Low Voltage Data Retention
Intersil CMOS RAMs are designed with battery backup in
mind. Data retention voltage and supply current are guaran-
teed over temperature. The following rules ensure data
retention:
1. Chip Enable (E) must be held high during data retention;
2. On RAMs which have selects or output enables (e.g., S,
1. In this mode, W rises after E. If W falls before E by a time exceeding TWLQZ (Max) TELQX (Min), and rises after E by a time exceeding
within V
G), one of the selects or output enables should be held in
TEHQZ (Max) TWHQZ (Min), then Q will remain in the high impedance state throughout the cycle.
CC
W
to V
Q
A
D
E
V
CC
E
CC
+0.3V.
(18) TAVEL
(Continued)
FIGURE 4. WRITE CYCLE 2: CONTROLLED BY E (EARLY WRITE)
4.5V
(15) TWLQZ
FIGURE 5. DATA RETENTION TIMING
(4) TELQX
V
CC
(20) TAVEH
DATA RETENTION
(21) TELEH
-0.3V TO V
HM-65262
V
(8) TAVAX
CC
(22) TWLEH
MODE
6-6
(23) TDVEH
2.0V
CC
3. Inputs which are to be held high (e.g., E) must be kept
4. The RAM can begin operation > 55ns after V
+0.3V
the deselected state to keep the RAM outputs high
impedance, minimizing power dissipation.
between V
up and down transitions.
the minimum operating voltage (4.5V).
CC
>55ns
+0.3V and 70% of V
4.5V
TEHDX
(24)
(7) TEHQZ
(19) TEHAX
(16) TWHQX
CC
during the power
CC
reaches