HM1-65162/883 Intersil Corporation, HM1-65162/883 Datasheet

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HM1-65162/883

Manufacturer Part Number
HM1-65162/883
Description
Manufacturer
Intersil Corporation
Datasheet

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March 1997
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143
Copyright © Intersil Americas Inc. 2002. All Rights Reserved
Features
• This Circuit is Processed in Accordance to MIL-STD-
• Fast Access Time . . . . . . . . . . . . . . . . . . . 70/90ns Max
• Low Standby Current. . . . . . . . . . . . . . . . . . . . 50µA Max
• Low Operating Current . . . . . . . . . . . . . . . . . 70mA Max
• Data Retention at 2.0V . . . . . . . . . . . . . . . . . . . 20µA Max
• TTL Compatible Inputs and Outputs
• JEDEC Approved Pinout (2716, 6116 Type)
• No Clocks or Strobes Required
• Wide Temperature Range . . . . . . . . . . -55
• Equal Cycle and Access Time
• Single 5V Supply
• Gated Inputs
Ordering Information
Pinouts
HM1-65162B/883
HM4-65162B/883
GND
DQ0
DQ1
DQ2
883 and is Fully Conformant Under the Provisions of
Paragraph 1.2.1.
- No Pull-Up or Pull-Down Resistors Required
A7
A6
A5
A4
A3
A2
A1
A0
70ns/20µA
HM-65162/883 (CERDIP)
10
11
12
1
2
3
4
5
6
7
8
9
TOP VIEW
HM1-65162/883
HM4-65162/883
|
Intersil (and design) is a trademark of Intersil Americas Inc.
TM
24
23
22
21
20
19
18
17
16
15
14
13
90ns/40µA
VCC
A8
A9
W
G
A10
E
DQ7
DQ6
DQ5
DQ4
DQ3
DQ0
NC
A6
A5
A4
A3
A2
A1
A0
HM1-65162C/883
10
11
12
13
5
6
7
8
9
90ns/300µA
14 15
o
4
C to +125
HM-65162/883 (CLCC)
3
-
TOP VIEW
16
2
HM-65162/883
17 18
o
1
C
188
32 31
Description
The HM-65162/883 is a CMOS 2048 x 8 Static Random
Access Memory manufactured using the Intersil Advanced
SAJI V process. The device utilizes asynchronous circuit
design for fast cycle time and ease of use. The pinout is the
JEDEC 24 pin DIP, and 32 pad 8-bit wide standard which
allows easy memory board layouts flexible to accommodate
a variety of industry standard PROMs, RAMs, ROMs and
EPROMs. The HM-65162/883 is ideally suited for use in
microprocessor based systems with its 8-bit word length
organization. The convenient output enable also simplifies
the bus interface by allowing the data outputs to be con-
trolled independent of the chip enable. Gated inputs lower
operating current and also eliminate the need for pull-up or
pull-down resistors.
19
TEMP. RANGE
-55
-55
o
o
20
30
C to 125
C to 125
29
28
27
26
25
24
23
22
21
A8
A9
NC
W
G
A10
E
DQ7
DQ6
o
o
C
C
CERDIP
CLCC
DQ0 - DQ7
VSS/GND
A0 - A10
PACKAGE
VCC
PIN
NC
W
E
G
2K x 8 Asynchronous
CMOS Static RAM
No Connect
Address Input
Chip Enable/Power Down
Ground
Data In/Data Out
Power (+5V)
Write Enable
Output Enable
DESCRIPTION
F24.6
J32.A
PKG. NO.
FN3001.1

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HM1-65162/883 Summary of contents

Page 1

... No Clocks or Strobes Required • Wide Temperature Range . . . . . . . . . . -55 • Equal Cycle and Access Time • Single 5V Supply • Gated Inputs - No Pull-Up or Pull-Down Resistors Required Ordering Information 70ns/20µA 90ns/40µA HM1-65162B/883 HM1-65162/883 HM4-65162B/883 HM4-65162/883 Pinouts HM-65162/883 (CERDIP) TOP VIEW VCC ...

Page 2

Functional Diagram ROW A4 ADDRESS A5 BUFFER HM-65162/883 128 X 128 ROW MEMORY ARRAY DECODER 128 128 COLUMN DECODER AND DATA INPUT / OUTPUT (X8 ...

Page 3

Absolute Maximum Ratings Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...

Page 4

TABLE 2. HM-65162/883 AC ELECTRICAL PERFORMANCE SPECIFICATIONS Device Guaranteed and 100% Tested. (NOTES 1, 2) PARAMETER SYMBOL CONDITIONS Read/Write/ (1) TAVAX VCC = 4.5V Cycle Time and 5.5V Address (2) TAVQV VCC = 4.5V Access Time and 5.5V Chip Enable ...

Page 5

TABLE 3. HM-65162/883 ELECTRICAL PERFORMANCE SPECIFICATIONS, AC AND DC PARAMETER SYMBOL CONDITIONS Input CIN VCC = Open, Capacitance F = 1MHz, All Measurements Referenced To Device Ground I/O CI/O VCC = Open, Capacitance F = 1MHz, All Measurements Referenced To ...

Page 6

Timing Waveforms ADDRESS G (6) TGLQX E Q NOTE High for a Read Cycle. Addresses must remain stable for the duration of the read cycle. To read, G and E must be ≤ VIL and W ≥ ...

Page 7

Timing Waveforms (Continued) ADDRESS this write cycle G has control of the output after a period, TGHQZ. G switching the output to a high impedance state allows data applied without bus ...

Page 8

Test Circuit DUT (NOTE 1) C NOTE: 1. Test head capacitance includes stray and jig capacitance. Burn-In Circuits HM-65162/883 CERDIP TOP VIEW A7 24 F10 ...

Page 9

... Intersil Corporation’s quality certifications can be viewed at www.intersil.com/design/quality Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use ...

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