HM1-6514B-9 INTERSIL [Intersil Corporation], HM1-6514B-9 Datasheet - Page 5

• Manufacturer Part Number: HM1-6514B-9
• Description: 1024 x 4 CMOS RAM
• Manufacturer: INTERSIL [Intersil Corporation]

Timing Waveforms
The address information is latched in the on-chip registers
on the falling edge of E (T = 0). Minimum address set up and
hold time requirements must be met. After the required hold
time, the addresses may change state without affecting
device operation. During time (T = 1) the output becomes
REFERENCE
REFERENCE
TIME
-1
0
1
2
3
4
5
TIME
DQ
W
A
E
TAVEL
(7)
HIGH Z
H
H
E
L
L
TEHEL
-1
(6)
INPUTS
VALID ADD
0
W
H
H
H
H
H
X
X
TELAX
(3) TELQX
(8)
(2) TAVQV
(2) TAVQY
(1) TELQV
FIGURE 1. READ CYCLE
A
X
V
X
X
X
X
V
TRUTH TABLE
HM-6514
1
6-5
DATA I/O
DQ
enabled, but data is not valid until during time (T = 2). W
must remain high throughout the read cycle. After the output
data has been read, E may return high (T = 3). This will dis-
able the output buffer and all inputs, and ready the RAM for
the next memory cycle (T = 4).
(5) TELEH
X
V
V
Z
Z
Z
Z
(17) TELEL
Memory Disabled
Cycle Begins, Addresses are Latched
Output Enabled
Output Valid
Read Accomplished
Prepare for Next Cycle (Same as -1)
Cycle Ends, Next Cycle Begins (Same as 0)
VALID DATA OUT
2
(4) TEHQZ
(7) TAVEL
FUNCTION
3
TEHEL
4
(6)
HIGH Z
NEXT ADD
5