VP305 MITEL [Mitel Networks Corporation], VP305 Datasheet - Page 5

• Manufacturer Part Number: VP305
• Description: Satellite Channel Decoder
• Manufacturer: MITEL [Mitel Networks Corporation]

DRAFT - PRELIMINARY DATA
VP305/6
LIST OF FIGURES.
Figure 1. VP305/6 Block Diagram................................................................................................... 7
Figure 2. System Application Diagram . ........................................................................................... 9
Figure 3. Carrier and Symbol synchronisation diagram.................................................................. 9
Figure 4. QPSK constellation.......................................................................................................... 10
Figure 5. Symbol filtering ................................................................................................................ 10
Figure 6. Frequency sweep generator ............................................................................................ 11
Figure 7. Viterbi block diagram showing error count generation..................................................... 14
Figure 8. Viterbi error count measurement ..................................................................................... 15
Figure 9. Viterbi error count coarse indication ................................................................................ 16
Figure 10. Conceptual diagram of the convolutional de-interleaver block ...................................... 17
Figure 11. Energy dispersal conceptual diagram............................................................................ 18
Figure 12. Eye diagram................................................................................................................... 34
Figure 13. SNR threshold vs Es / No ............................................................................................. 36
Figure 14. Carrier sweep rise and fall times vs. CR_OFFSET........................................................ 38
Figure 15. Carrier phase error detector gain...................................................................................40
Figure 16. Carrier sweep rate for a delta frequency of ±10MHz. .................................................... 43
Figure 17. Parallel interface write cycle action diagram.................................................................. 61
Figure 18. Parallel interface read cycle action diagram .................................................................. 63
Figure 19. I²C bus timing................................................................................................................. 65
Figure 20. Parallel interface write cycle timing diagram.................................................................. 66
Figure 21. Parallel interface read cycle timing diagram .................................................................. 66
Figure 22. VP305/6 data input timing diagram................................................................................ 67
Figure 23. VP305/6 Transport Packet Header bytes ...................................................................... 68
Figure 24. VP305/6 output data wave form diagram ...................................................................... 69
Figure 25. VP305/6 data output timing diagram ............................................................................. 70
Figure 26. Crystal oscillator circuit. ................................................................................................. 73
Figure 27. Pin connections - top view ............................................................................................. 79
The duplication or disclosure of data contained on this sheet is subject to the restrictions
on the title page of this document.
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