VP305 MITEL [Mitel Networks Corporation], VP305 Datasheet
VP305
Available stocks
Related parts for VP305
VP305 Summary of contents
Page 1
... The copyright and the foregoing restriction on reproduction and use extend to all media in which the media may be embodied. The VP305 decoder for digital satellite television transmissions to the European Broadcast Union ETS 300 421 specification (ref. 1). They receive digitised I and Q signals from the tuner, demodulate the QPSK data and provide a complete Forward Error Correction, (FEC) and de- scrambling function ...
Page 2
... VP305/6 DRAFT - PRELIMINARY DATA CONTENTS. 1. FUNCTIONAL DESCRIPTION. ..............................................................................................7 1.1. System overview. ..........................................................................................................7 1.2. The QPSK Demodulator block. .....................................................................................9 1.2.1. Input requirements. .............................................................................................10 1.2.3. Matched filters.....................................................................................................10 1.2.4. Decimation filters.................................................................................................10 1.2.5. Carrier frequency synchronisation ......................................................................11 1.2.6. Symbol synchronisation and tracking..................................................................12 1.3. The Viterbi Decoder block. ............................................................................................13 1.3.1. Viterbi error count measurement.........................................................................14 1.3.2. Viterbi error count coarse indication....................................................................15 1.4. The De-interleaver block. ..............................................................................................16 1 ...
Page 3
... VIT_CTRL1: Viterbi control synchronisation byte register 1 ............................. 50 2.11.2. VIT_CTRL2: Viterbi control synchronisation byte register 2 ............................. 51 2.11.3. IE_FEC: Interrupt FEC register......................................................................... 52 2.11.4. STAT_EN: Status enable register..................................................................... 53 2.11.5. GEN_CTRL: General control register. .............................................................. 54 The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. VP305/6 3 ...
Page 4
... Parallel interface Read cycle timing. .............................................................................66 4.4. Data input timing. ..........................................................................................................67 5. MPEG PACKET DATA OUTPUT...........................................................................................68 5.1. Data output format.........................................................................................................68 5.2. Data output timing. ........................................................................................................70 6. VP305/6 OPERATING CONDITIONS. ...................................................................................71 6.1. Recommended operating conditions.............................................................................71 6.2. Electrical characteristics................................................................................................72 6.3. Crystal specification. ..................................................................................................... 73 6.4. Absolute maximum ratings. ...........................................................................................73 6.5. Pinout description..........................................................................................................74 6.6. Alphabetical listing of the pinout....................................................................................77 6.7. Numerical listing of the pinout. ......................................................................................78 7 ...
Page 5
... Figure 21. Parallel interface read cycle timing diagram .................................................................. 66 Figure 22. VP305/6 data input timing diagram................................................................................ 67 Figure 23. VP305/6 Transport Packet Header bytes ...................................................................... 68 Figure 24. VP305/6 output data wave form diagram ...................................................................... 69 Figure 25. VP305/6 data output timing diagram ............................................................................. 70 Figure 26. Crystal oscillator circuit. ................................................................................................. 73 Figure 27. Pin connections - top view ............................................................................................. 79 The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document ...
Page 6
... VP305/6 DRAFT - PRELIMINARY DATA LIST OF TABLES. Table 1. Decimation ratios...............................................................................................................11 Table 2. Viterbi decoder input format ..............................................................................................13 Table 3. Viterbi decoder code rate ..................................................................................................13 Table 4. De-interleaver data sequence ...........................................................................................17 Table 5a. BANK Register ................................................................................................................20 Table 5b. Register bank 0. BANK[5: ......................................................................................20 Table 5c. Register bank 1. BANK[5:3] = 8....................................................................................... 20 Table 5d. Register bank 2. BANK[5: ....................................................................................21 Table 5e ...
Page 7
... The VP305/6 contains three phase lock loop systems for control of the voltage controlled oscillators in the SL1710, the VP216/7 and an internal numerically controlled oscillator (NCO) in the VP305/6. The NCO can be set to provide a triangular wave form frequency search to establish symbol lock. There are also two AGC systems in the VP305/6, one controlling the SL1710 gain and a second internal AGC control of the output power levels from the QPSK block to the Viterbi block ...
Page 8
... The code range is, from 000000 = least positive valid output, to 111111 = most positive valid output. These six bit data channels are input to the VP305/6 on the IIN and QIN pins to the QPSK demodulator block, see figure 2 on page 9. There the data is decimated and filtered to obtain the soft decision symbol data to pass to the Viterbi decoder ...
Page 9
... FILTER 14.984375MHz LOOP FILTER AGC LOOP FILTER MICROPROCESSOR IIN VP216/7 QIN DUAL ADC VCO SYS_CLK SYM_NF LOOP SYM_VCO FILTER SYM_RP XTI CR_RP CR_VCO CR_U/LSWL PSCAL VP305/6 IIN QIN VP305/6 SYS_CLK SYM_VCO PSCAL CR_VCO AGC_OUT VP305/6 VCO CONV SWEEP GEN CONV AFC 9 ...
Page 10
... The sample rate at the input to the matched filter is equal to twice the symbol rate, 2Rs. The SYM_DR bits in the SYM_CONFIG register can be programmed to allow for the following filtered symbol rates at the input to the VP305/6: 2Rs, 3Rs, 4Rs, where Rs = symbol rate. IIN ...
Page 11
... The SL1710 local oscillator frequency of 479.5MHz is maintained by a frequency synthesis loop on the VP305/6. The SL1710 voltage controlled oscillator (VCO) frequency is divided internally generate a push-pull feedback reference frequency signal. This is connected to the VP305/6 PSCAL PECL inputs and then to the CR_U/LSWL dividers. The output from the CR_U/LSWL dividers is compared with the crystal oscillator frequency divided by the CR_RP division ratio ...
Page 12
... SYM_NF and SYM_RP division ratios to match the decimation rate chosen. The VP216/7 voltage controlled oscillator (VCO) frequency is connected to the VP305/6 SYS_CLK input and then to the SYM_NF divider. The output from the SYM_NF divider is compared with the crystal oscillator frequency divided by the SYM_RP division ratio. A push-pull feedback signal (SYM_VCO) is output to an active filter to complete the loop and control the VP216/7 VCO, see Fig ...
Page 13
... 2 1010 1111 3 101 110 10101 11010 7 1000101 1111010 VP305/6 13 ...
Page 14
... The VIT ERR H-M-L group of three registers is programmed with required number of data bits (the error count period) (VITEP[23:0]). The actual value is four times VITEP[23:0]. The count of errors found during this period is loaded by the VP305/6 into the VIT ERR C H-L pair of registers when the bit count VITEP[23:0] is reached. At the same time an interrupt is generated on the IRQ line. ...
Page 15
... This VERR mode is enabled by setting the INTVIS bit in the TEST2 register. Figure 9 below shows the bit errors rising to the maximum programmed value and triggering a change of state on the VERR line. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. VITEP[23:0] VERRC[15:0] VITEP[23:0] . VP305/6 DATA BITS 15 ...
Page 16
... Only when the FIFOs are full, will the read out of the 204 byte message be enabled. On the VP305/6, this function is realised in random access memory (RAM) with some spare capacity to avoid messages being over written before they are read out ...
Page 17
... VP305 ...
Page 18
... VP305/6 DRAFT - PRELIMINARY DATA 1.5. The Reed Solomon block. In the Transmission system, the MPEG2 message packet is encoded using the Reed Solomon RS(204,188, T=8) shortened code. This converts the 188 byte data packet into a Reed Solomon encoded block containing 204 bytes. The 16 check bytes allow the decoding system to search the packet for errors and correct up to eight bytes containing errors ...
Page 19
... Microprocessor interface. This interface can be either a serial I²C bus or a parallel interface port, see section 3 starting on page 58. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. VP305/6 19 ...
Page 20
... VP305/6 DRAFT - PRELIMINARY DATA 2. REGISTER DETAILS 2.1. Parallel interface register map. The default state of almost all of the registers is zero, except the ID register and unused registers. Reserved or unused bits should be set to zero when writing to a register. NAME ADR D7 BANK 0 Reserved Table 5a. BANK Register 0. (Address byte = 0, Data byte = NEXT BANK ) ...
Page 21
... CR_LSWL[13:8] Carrier Lower sweep limit (upper nibble) CR_LSWL[7:0] Carrier Lower sweep limit (lower byte) CR_CONFIG[7:0] Carrier configuration CONFIG[7:0] Configuration ID[7:0] Chip identification VERRC[15:8] - Viterbi error count high byte VERRC[7:0] - Viterbi error count low byte RSUBC[7:0] - Reed Solomon uncorrected block count VP305 R/W R R/W R/W R/W R/W R/W R/W ...
Page 22
... VP305/6 DRAFT - PRELIMINARY DATA NAME ADR VIT_MODE 1 IQSWAP F_LOCK VIT_ERR H 2 VIT_ERR M 3 VIT_ERR L 4 VI_MAX_ERR 5 VI_BER_PER 6 VBPER[7:0] - Viterbi bit error rate based synchronisation period VI_BER_LIM 7 VBLIM[7:0] - Viterbi bit error rate based synchronisation limit Table 5g. Register bank 5. BANK[5:3] = 40. NAME ADR ...
Page 23
... DRAFT - PRELIMINARY DATA 2.2. Serial interface register map. Not available on VP305. The default state of all registers is reset to 0. Reserved or unused bits should be set to zero when writing to a register. All values are shown as decimal numbers, unless otherwise defined. NAME ADR D7 RADD IAI AD6 ...
Page 24
... VP305/6 DRAFT - PRELIMINARY DATA NAME ADR ID[7:0] Chip identification. Writing to this address will have no effect. VIT_ERR_C H 33 VIT_ERR_C L 34 RS_UBC 35 Not used 33-35 Not used 36-39 Writing to these addresses will have no effect. Reading will return 255 ID 40 ID[7:0] Chip identification. Writing to this address will have no effect. ...
Page 25
... Reserved AD5 AD[2:0] Reserved - not used. If these bits are written they are ignored by the VP305/6. This allows the microprocessor to write the BANK address with the serial mode register address. AD[5:3] Bank address These are the active bits in the register. See table 7 below for details. ...
Page 26
... VP305/6 DRAFT - PRELIMINARY DATA 2.4. RADD: I²C Register address - Serial mode only. Not available on VP305. RADD is the I²C register address the first byte written after the VP306 I²C chip address when in write mode. To write to the chip, the microprocessor should send a START condition and the chip address with the write bit set, followed by the register address where subsequent data bytes are to be written ...
Page 27
... ID[7:0] Identification VP305/6 version. 2.5.2. INT_QPSK: Interrupt for QPSK block, register. These bits indicate the QPSK block event causing the interrupt signalled by the IRQ line going low. The IRQ line is reset high and the register is reset to zero when the INT_QPSK register is read. The events can be masked from activating both the INT_QPSK register bit and the IRQ line by setting the appropriate event masking bit LOW in the IE_QPSK (interrupt enable) register, see page 31 ...
Page 28
... VP305/6 DRAFT - PRELIMINARY DATA 2.5.3. INT_FEC: Interrupt FEC register. These bits indicate the FEC block event causing the interrupt signalled by the IRQ line going low. The IRQ line is reset high and the register is reset to zero when it is read. The events can be masked from activating the IRQ line by setting the appropriate event masking bit in the IE_FEC (interrupt enable) FEC register, see page 52 ...
Page 29
... High = Viterbi bit lock detector in lock. Low = Viterbi bit lock detector out of lock. STATUS[6] High = Frame align detector in lock. Low = Frame align detector out of lock. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. Type Read STATUS[6:0] VP305 ...
Page 30
... VP305/6 DRAFT - PRELIMINARY DATA 2.5.5. AGC_LVL: AGC loop voltage meter register. Parallel mode - Bank 0. Address 4. Type Read. Serial mode - Address 04 AGC_LVL[7:0] AGC loop voltage meter AGC_LVL[7:0] AGC loop voltage meter. The register is NOT reset to zero when it is read. The relationship between the loop voltage Vagc and the AGC_LVL register is: ...
Page 31
... IE_QPSK[6] High = Enable Frequency sweep has reached its lower limit indication in INT_QPSK register. IE_QPSK[7] High = Enable Frequency sweep has reached its upper limit indication in INT_QPSK register. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document (default state) VP305 ...
Page 32
... VP305/6 DRAFT - PRELIMINARY DATA 2.6. BANK 1: Program QPSK registers. 2.6.1. SYM_CONFIG: Symbol configuration register. Parallel mode - Bank 1. Address 1. Type Read / Write. Serial mode - Address 09 Reserved SYM_CONFIG[1:0] SYM_DR[1:0] Filtered decimation ratio select decimation (over sampling ratio = decimation by 1/2 (over sampling ratio = decimation by 2/3 (over sampling ratio = 3) See also SYM_RATIO: Input decimation factor register, page 34 ...
Page 33
... This is the division ratio for the Symbol clock input from the ADC VCO. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document SYM_RP[3:0] Symbol AFC reference period Type Read / Write VP305 ...
Page 34
... VP305/6 DRAFT - PRELIMINARY DATA 2.6.4. SYM_RATIO: Symbol input decimation factor register. Parallel mode - Bank 1. Address 5. Type Read / Write. Serial mode - Address 13 Reserved SYM_RATIO[2:0] SYM_RATIO[2: 2.6.5. AGC_REF: Reference AGC level registers. Parallel mode - Bank 1. Address 6. Type Read / Write. ...
Page 35
... Low = Disable internal DC offset compensation on I and Q channels. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document 0.6 AGC_REF = 233 84 0.3 AGC_REF = 233 84 INT_DC Symbol rate Rs MSym/s > Reserved VP305 AGC_BW[1:0] 35 ...
Page 36
... VP305/6 DRAFT - PRELIMINARY DATA 2.7. BANK 2: Program QPSK registers. 2.7.1. SCALE: IOUT and QOUT outputs, scale factor register. Parallel mode - Bank 2. Address 1. Type Read / Write. Serial mode - Address 17 SCALE[7:0] Scale factor for IOUT and QOUT outputs SCALE[7:0] Scale factor for IOUT and QOUT outputs. The value in the SCALE register adjusts the matched filter outputs before the signal is truncated to 3 bits ...
Page 37
... T negative lengthenes the T and shortens the T rise The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document Moving CR_OFFSET more rise fall and visa versa. fall VP305 ...
Page 38
... VP305/6 DRAFT - PRELIMINARY DATA 350 325 300 275 250 225 T ris e 200 175 150 125 100 -140 -120 -100 -80 -60 -40 -20 Fig. 14 Carrier sweep rise and fall times vs. CR_OFFSET.. 2.7.3.1. Acquisition Phase. To calculate the DC offset value required, the period of each ramp should be measured and used ...
Page 39
... VCO frequency (PSCAL pins). The register value sets the 4 most significant bits bit counter. The actual count is CR_RP[3:0] * 1024. See page 12 for further discussion. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document CR_RP[3:0] Carrier reference period VP305 ...
Page 40
... VP305/6 DRAFT - PRELIMINARY DATA 2.7.5. CR_KP: Carrier loop filter gain (P term) register. Parallel mode - Bank 2. Address 5. Type Read / Write. Serial mode - Address 21 CR_KP[7:0] Carrier loop filter gain (P term) CR_KP[7:0] Carrier loop filter gain (P term) This term, CR_KP * 2 determines the resolution of the Sigma Delta conversion. It should be > ...
Page 41
... Carrier lock detector threshold. This should be set to correspond to the phase lock detector length set by bit 4 of the CONFIG register, see page 45. CONFIG[ The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document CR_THSL 31 72 VP305 ...
Page 42
... VP305/6 DRAFT - PRELIMINARY DATA 2.8. BANK 3: Program QPSK registers. 2.8.1. CR_SWR: Carrier sweep rate register. Parallel mode - Bank 3. Address 1. Type Read / Write. Serial mode - Address 25 CR_SWR[7:0] Carrier sweep rate CR_SWR[7:0] Carrier sweep rate. CR_SWP = DCR Where the carrier phase detector gain, typically 10 for low dB. ...
Page 43
... SL1710. See page 12 for further discussion. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 100 120 140 160 180 Type Read / Write VP305/6 200 220 240 260 ...
Page 44
... VP305/6 DRAFT - PRELIMINARY DATA 2.8.3. CR_LSWL U & L: Carrier Lower sweep limit registers. Parallel mode - Bank 3. Addresses 4, 5. Serial mode - Addresses 28, 28 Reserved CR_LSWL[13:8] Carrier Lower sweep limit (upper nibble) CR_LSWL[7:0] Carrier Lower sweep limit (lower byte) These two bytes together form the 14 bit number: CR_LSWL[13:0] Carrier Lower sweep limit. This is the division ratio (lower) for the prescaler input (PSCAL) from the SL1710 ...
Page 45
... See also CR_THSL register on page 41. CONFIG[5] Reserved set low. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document CONFIG[7:0] Offset 2's Complement CONFIG[ 000000 100000 000001 100001 011111 111111 100000 000000 100001 000001 111110 011110 111111 011111 VP305 ...
Page 46
... VP305/6 DRAFT - PRELIMINARY DATA CONFIG[6] Constellation selector. High = BPSK. Low = QPSK.. CONFIG[7] SNR Estimator on/off. High = used. Low = off. 2.9. BANK 4: Monitor FEC read registers. 2.9.1. VIT_ERR_C H & L: Viterbi error count registers. Parallel mode - Bank 4. Addresses 1, 2. Serial mode - Addresses 33, 34 VERRC[15:8] - Viterbi error count high byte ...
Page 47
... See section 2.10.5 on page 49 for an explanation on how to use this bit. IQSWAP Swap High = I lags Q. Low = I leads Q. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. Type Read / Write Reserved VITCR[2:0] - code rate code rate 1/2 2/3 3/4 5/6 7/8 1/2 1/2 1/2 VP305 ...
Page 48
... VP305/6 DRAFT - PRELIMINARY DATA 2.10.2. VIT_ERR H, M & L: Viterbi error period registers. Parallel mode - Bank 5. Addresses Serial mode - Addresses 42, 43, 44 VITEP[23:16] - Viterbi error period high byte VITEP[15:8] - Viterbi error period middle byte VITEP[7:0] - Viterbi error period low byte These three bytes together form the 24 bit number: VITEP[23:0] Viterbi error period, effectively the number of valid data bits, during which an error count is accumulated ...
Page 49
... Coding rate 1/2 2/3 3/4 5/6 7/8 Table 9. Viterbi bit error rate threshold. . The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document min. max. 0.090 0.120 0.055 0.070 0.035 0.050 0.020 0.035 0.010 0.025 VP305 ...
Page 50
... VP305/6 DRAFT - PRELIMINARY DATA 2.11. BANK 6: Program FEC and general control registers. 2.11.1. VIT_CTRL1: Viterbi control synchronisation byte register 1 Parallel mode - Bank 6. Address 1. Type Read / Write. Serial mode - Address 49 BS_MODE[1:0] VBIT_MV[1:0]Viterbi synchronisation majority voting selection for the number of correct bits in a byte to have the byte labelled as a synchronisation byte ...
Page 51
... These bits are reserved for test applications. For normal operation, they must be set to zero. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document VS_LK[2:0] No. syncs for lock Recommended 6 7 Not valid Not valid VP305 ...
Page 52
... VP305/6 DRAFT - PRELIMINARY DATA 2.11.3. IE_FEC: Interrupt FEC register. When the bits of this register are set high, they enable an event signalled in the INT_FEC register to generate an interrupt on the IRQ pin. They do not affect the setting of bits in the INT_FEC register, see page 28. Parallel mode - Bank 6 ...
Page 53
... STAT_EN[5] High = Enable Viterbi bit lock detect signal on the STATUS pin. STAT_EN[6] High = Enable Frame alignment lock detect signal on the STATUS pin. STAT_EN[7] High = Enable symbol clock signal on the STATUS pin. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document VP305 ...
Page 54
... VP305/6 DRAFT - PRELIMINARY DATA 2.11.5. GEN_CTRL: General control register. Parallel mode - Bank 6. Address 5. Type Read / Write. Serial mode - Address 53 NSYNC[1:0] The number of successive incorrect synchronising bytes in N successive blocks before byte lock in the descrambler is lost. The value programmed is related shown in the following truth table ...
Page 55
... High = Partial reset of the De scramble block with its synchronising function. Low = No reset. RES High = Reset the complete chip, except for the microprocessor interface, to its default state. Low = No reset. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document PR_DS PR_BS FR_QP VP305 PR_QP 55 ...
Page 56
... VP305/6 DRAFT - PRELIMINARY DATA 2.12. BANK 7: Program test registers. 2.12.1. TEST1: Test 1 register - for diagnostic / qualification purposes only. Parallel mode - Bank 7. Address 1. Type Read / Write. Serial mode - Address 57 TEST1[7:0] Set all bits low for normal operation. 2.12.2. TEST2: Test 2 register - for diagnostic / qualification purposes only. ...
Page 57
... TEST3: Test 3 register - for diagnostic / qualification purposes only. Parallel mode - Bank 7. Address 3. Type Read / Write. Serial mode - Address 59 TEST3[7:0] Set all bits low for normal operation. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document Reserved VP305 ...
Page 58
... SER 0 1 3.1. I²C bus Interface. Not available on VP305. The I²C bus serial interface (ref. 2.) uses pins: SDA Serial data, the most significant bit is sent first. SCL Serial clock (D0). The I²C bus Address is 0001 110 The circuit works as a slave transmitter with the eighth bit set high slave receiver with the eighth bit set low ...
Page 59
... RADD ADDRESS (n) Write/read/write operation with repeated start and auto increment off with IAI set high - VP305 slave transmitter. This example uses the GPP_CTRL register which has a read bit 0 and write bits Register address 128 (IAI). S DEVICE W A RADD A S DEVICE R A DATA NA S DEVICE W A DATA A P ...
Page 60
... A write cycle starts with the master indicating its intent by setting write and placing a valid address on A2:0 and asserting AS . The VP305/6 takes the assertion the start of a cycle and latches the address on A2:0 by the falling edge AS . This event also causes VP305/6 to respond to the request by the master to send data, WHEN IT CAN, by asserting DTACK . The The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document ...
Page 61
... Notice that there is no maximum time specified from the assertion the assertion of DTACK . It is assumed that the master will insert wait states/cycles until DTACK is recognised. When the master negates CS the VP305/6 will latch the data on D7:0 on the rising edge When the master negates CS the VP305/6 will then negate DTACK . A2:0 ...
Page 62
... VP305/6 DRAFT - PRELIMINARY DATA Write cycle flowchart. Bus master Address the VP305/6 Set R/W to Write Place address on A2:0 Assert Address Strobe Place data on D7:0 Assert Chip Select Transfer the data De-Assert Chip Select Terminate the cycle De-Assert Address Strobe Remove Data from D7:0 Set R/W to Read ...
Page 63
... A read cycle starts with the master indicating its intent by setting read and placing a valid address on A2:0 and asserting AS . The VP305/6 takes the assertion the start of a cycle and latches the address on A2:0 by the falling edge AS . This event also causes VP305/6 to respond to the data request, WHEN IT CAN, by placing valid data on the data bus and asserting DTACK , informing the master that it may proceed ...
Page 64
... VP305/6 DRAFT - PRELIMINARY DATA Read cycle flowchart. Bus master Address the VP305/6 Set R/W to Read Place address on A2:0 Assert Address Strobe Assert Chip Select Acquire the data Latch data De-Assert Chip Select De-Assert Address Strobe Start next cycle The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document ...
Page 65
... SU;STA Fig. 19. I²C bus timing. Symbol f SCL t BUFF t HD;STA t LOW t HIGH t SU;STA t HD;DAT t SU;DAT SU;STO Table 15. I²C bus timing . VP305 SU;STO Value Unit Min Max. 0 450 kHz 200 ns 200 ns 450 ns 600 ns 200 ns 100 ns 100 ns note 1 ns ...
Page 66
... VP305/6 DRAFT - PRELIMINARY DATA 4.2. Parallel interface Write cycle timing. A2:0 t AVASL R/W t WVASL AS CS DTACK D7:0 Fig. 20. Parallel interface write cycle timing diagram. 4.3. Parallel interface Read cycle timing. A2:0 t AVASL R/W t RVASL AS CS DTACK D7:0 Fig. 21. Parallel interface read cycle timing diagram . The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document ...
Page 67
... Chip Select High to Data Invalid CSHDI 4.4. Data input timing Fig. 22. VP305/6 data input timing diagram . Parameter Data intput delay The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. Min. ...
Page 68
... TEI MDO[7] Fig. 23. VP305/6 Transport Packet Header bytes . After decoding, the 188 byte MPEG packet is output on the MDO pins in 188 consecutive clock cycles. Additionally, when the ENTEI bit in the GEN_CTRL register is set high, any decoded packets with uncorrectable bytes will automatically set the TEI bit in the MPEG header, see page 54. ...
Page 69
... MOVAL BKERR Tp Fig. 24. VP305/6 output data wave form diagram. MCLK will be a continuously running clock once symbol lock has been achieved in the QPSK block and is derived from the symbol clock. MCLK is the output interface byte rate clock, running at a rate given by the table on page 70. The maximum jitter in the packet synchronisation byte is limited to one output clock period ...
Page 70
... The Viterbi code rate is programmed in the VIT_MODE register, see page 47. 5.2. Data output timing. MCL Fig. 25. VP305/6 data output timing diagram. Parameter Data output delay The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document ...
Page 71
... DRAFT - PRELIMINARY DATA 6. VP305/6 OPERATING CONDITIONS. 6.1. Recommended operating conditions. Parameter Power supply voltage Power supply current Input clock frequency ¹ PSCAL input frequency Sytem clock input frequency SCL clock frequency Ambient operating temperature Table 18. Recommended operating conditions . Note 1. When not using a crystal, XTI may be driven from an external source over the frequency range shown ...
Page 72
... VP305/6 DRAFT - PRELIMINARY DATA 6.2. Electrical characteristics. Test conditions (unless otherwise stated): As specified in Recommended Operating Conditions. DC CHARACTERISTICS Parameter Digital Inputs CMOS compatible Input high voltage Input low voltage Digital Inputs TTL compatible Input high voltage Input low voltage Leakage current - All inputs ...
Page 73
... The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. XTO 33pF Fig. 26. Crystal oscillator circuit. -0·3V to +3.63V -0·3V to 5V+0·3VV DD -0· +0·3V DD 0°C to +70°C -65°C to 150°C VP305/6 9.99 to 16.00MHz. ± 25ppm. ± 50ppm. 30pF. <35 73 ...
Page 74
... D7:0 Data port for read or write data SCL Clock input 42-43 for I²C when SER = logic 0. 44 SDA Data I/O pin for I²C. Not available on VP305 version. 45 RESET Active HIGH reset input, with 100k pull down resistor. 48 XTO Crystal output. An internal feedback resistor to XTI is included ...
Page 75
... VCO frequency. 100 TEST3 For factory test only. This pin must be connected to VSS in normal operation. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. VP305/6 O Tri- 3.3 1 state O Tri- 3.3 1 state ...
Page 76
... All pins must be connected. 29,40,46, 52,58,66, 72,79,85, 92,99 The remaining pins 71, 73, 94 and 95 are N/C - not connected internal to the VP305/6. They may be connected external to the VP305/6. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. 76 Table 20. Pinout details . ...
Page 77
... TEST1 75 63 TEST2 77 64 TEST3 100 69 XTI 48 67 XTO 49 71 VDD 2 73 VDD 12 94 VDD 20 95 VDD 28 4 VDD 34 5 VDD 41 VP305/6 PIN VDD 47 VDD 53 VDD 59 VDD 65 VDD 70 VDD 74 VDD 78 VDD 86 VDD 93 VDD 98 VERR 76 VSS 3 VSS 13 VSS 21 VSS 29 VSS 40 VSS ...
Page 78
... VP305/6 DRAFT - PRELIMINARY DATA 6.7. Numerical listing of the pinout. PIN FUNCTION PIN 1 SER 26 2 VDD 27 3 VSS 28 4 PSCAL 29 5 PSCAL 30 6 IIN5 31 7 IIN4 32 8 IIN3 33 9 IIN2 34 10 IIN1 35 11 IIN0 36 12 VDD 37 13 VSS 38 14 QIN5 39 15 QIN4 40 16 ...
Page 79
... DRAFT - PRELIMINARY DATA 100 Fig. 27. Pin connections - top view. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. VP305 GH100 50 79 ...
Page 80
... VP305/6 DRAFT - PRELIMINARY DATA 7. REFERENCES. 1. European Digital Video Broadcast Standard, ETS 300 421 December 1994. ETS Secretariat 06921 Sophia Antipolis Cedex France. 2. Purchase of Mitel I²C components conveys a licence under the Philips I²C Patent Rights to use these components in I²C systems, provided that the systems conform to the I² ...
Page 81
... On chip error rate monitor. SYNCHRONISATION CONTROL Automatic synchronisation. DE-INTERLEAVER Forney with depth 12. REED SOLOMON Conforms to EBU specification. DESCRAMBLER EBU specification Descrambler. Ordering information. VP306 GP1N. The duplication or disclosure of data contained on this sheet is subject to the restrictions on the title page of this document. VP305/6 81 ...
Page 82
... CR_SWR = 150. 9.2. Lock acquisition algorithm. The Symbol loop phase lock acquisition is automatically handled in the VP305/ initiated by turning on the carrier sweep function with the carrier loop open. The NDAML carrier phase detector is enabled. These three items are selected in CR_CONFIG[2:0] register 30. Next the carrier loop is closed and a program loop started to detect when lock occurs ...
Page 83
...
Page 84
...
Page 85
North America Tel: +1 (770) 486 0194 Fax: +1 (770) 631 8213 Information relating to products and services furnished herein by Mitel Corporation or its subsidiaries (collectively “Mitel”) is believed to be reliable. However, Mitel assumes no liability for errors ...