MFR4200MAE40 FREESCALE [Freescale Semiconductor, Inc], MFR4200MAE40 Datasheet - Page 253

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MFR4200MAE40

Manufacturer Part Number
MFR4200MAE40
Description
FlexRay Communication Controllers
Manufacturer
FREESCALE [Freescale Semiconductor, Inc]
Datasheet

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Figure 8-14 (PS V1.1): In MFR4200 the check of
correction rather than after external rate correction.
C.8.7
Figure 8-15 (PS V1.1): The implementation in MFR4200 is compliant with the red text in the middle of
the diagram. Moreover, when macrotick counting is reset, the host interface indication of
immediately reset to 0, as soon as the macrotick counting is reset; however, internally, the macrotick
generation continues for a short time in accordance with the specification.
C.8.8
Table 8-3 (PS V1.1): MFR4200 supports up to 16 sync frames, rather than 15.
C.9
The implementation of the host interface is compliant with the specification in PS V1.1. The
implementation supports the following features:
C.10
MFR4200 supports supervision of voltage levels, and performs a reset when the supply voltage drops
below a boundary specified in
A low power mode or sleep mode is not supported.
C.11
The implementation is compliant with PS V1.1.
Freescale Semiconductor
Message filtering
— Frame ID filtering
— Cycle counter filtering
— Channel filtering
— Message ID filtering (FIFO only)
Message FIFO (receive FIFO)
Timer
Error signalling
Host interrupts
— Timer interrupt
— Error signaling interrupt
Network management vector
Controller Host Interface
Device Specific Power Modes
Bus Guardian Schedule Monitoring
Clock Correction
Sync Frame Configuration Rules
Chapter 5, “Clocks and Reset
MFR4200 Data Sheet, Rev. 0
vRateCorrection
Generator.
is performed before the external offset
Controller Host Interface
vMacrotick
is
253

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