MFR4200MAE40 FREESCALE [Freescale Semiconductor, Inc], MFR4200MAE40 Datasheet - Page 124

• Manufacturer Part Number: MFR4200MAE40
• Description: FlexRay Communication Controllers
• Manufacturer: FREESCALE [Freescale Semiconductor, Inc]

MFR4200 FlexRay Communication Controller
3.2.3.6.15
Address 0x33C
Reset
The EMCR and OMCR are described in the following section.
3.2.3.6.16
Address 0x33E
Reset
The EMCR and OMCR hold the number of valid sync frames received during the static segment of an even
or odd cycle, respectively. If sync frame filtering is enabled, only sync frames that have passed the sync
frame rejection and/or acceptance filters (see
(SYNFRFR)” and
considered. The EMCR and OMCR registers hold the number of valid measurements in the measurement
tables (see
Section 3.2.3.6.11, “Odd Measurement Channel A n Register, n = [0:15]
value of EMCR is two, then two valid sync frames are available for clock sync calculations; the remaining
fourteen values in the measurement table for the even cycle are invalid and may have undefined content.
The EMCR and OMCR counters are incremented each time, when a valid sync frame has been received
on at least one of the channels.
EMCR and OMCR are reset when the CC enters the initialize schedule and coldstart collision resolution
states. In the normal active state and the normal passive state, EMCR is reset in the NIT of the odd cycle,
and OMCR is reset at the end of the even cycle. If the node is a non sync node, EMCR and OMCR are
124
Reserved
Reserved
Reserved
Reserved
15
15
7
7
r
r
r
r
undefined state
undefined state
Section 3.2.3.6.9, “Odd Sync Frame ID n Register, n = [0:15]
Even Measurement Counter Register (EMCR)
Odd Measurement Counter Register (OMCR)
Reserved
Reserved
Reserved
Reserved
14
14
Section 3.2.3.8.1, “Sync Frame Acceptance Filter Value Register
6
6
r
r
r
r
Figure 3-87. Even Measurement Counter Register
Figure 3-88. Odd Measurement Counter Register
Reserved
Reserved
Reserved
Reserved
13
13
5
5
r
r
r
r
MFR4200 Data Sheet, Rev. 0
Reserved
Reserved
Reserved
Reserved
12
12
Section 3.2.3.8.3, “Sync Frame Rejection Filter Register
4
4
r
r
r
r
Reserved
Reserved
OMC3
EMC3
11
11
rh
rh
3
3
r
r
Reserved
Reserved
OMC2
EMC2
10
10
rh
rh
2
2
(OMAnR)”). For example, if the
r
r
(OSFIDnR)” and
Reserved
Reserved
OMC1
EMC1
Freescale Semiconductor
(SYNFAFVR)”) are
rh
rh
9
1
9
1
r
r
Reserved
Reserved
OMC0
EMC0
rh
rh
8
0
8
0
r
r