MACH111-14 AMD [Advanced Micro Devices], MACH111-14 Datasheet - Page 9

• Manufacturer Part Number: MACH111-14
• Description: High-Performance EE CMOS Programmable Logic
• Manufacturer: AMD [Advanced Micro Devices]

The Macrocell
The MACH111 macrocells can be configured as either registered or combinatorial, with
programmable polarity. The macrocell provides internal feedback whether configured as
registered or combinatorial. The flip-flops can be configured as D-type or T-type, allowing for
product-term optimization.
The flip-flops can individually select one of four clock pins, which are also available as data inputs.
The registers are clocked on the LOW-to-HIGH transition of the clock signal. The flip-flops can also
be asynchronously initialized with the common asynchronous reset and preset product terms.
The I/O Cell
The I/O cell in the MACH111 consists of a three-state output buffer. The three-state buffer can
be configured in one of three ways: always enabled, always disabled, or controlled by a product
term. If product term control is chosen, one of two product terms may be used to provide the
control. The two product terms that are available are common to eight I/O cells. Within each
PAL block, two product terms are available for selection by the first eight three-state outputs;
two other product terms are available for selection by the last eight three-state outputs.
SpeedLocking for Guaranteed Fixed Timing
The unique MACH 1 & 2 architecture is designed for high performance—a metric that is met in
both raw speed, but even more importantly, guaranteed fixed speed. Using the design of the
central switch matrix, the MACH111 product offers the SpeedLocking feature, which allows a
stable fixed pin-to-pin delay, independent of logic paths, routing resources and design refits for
up to 12 product terms per output. Other non-Vantis CPLDs incur serious timing delays as
product terms expand beyond their typical 4 or 5 product-term limits. Speed and SpeedLocking
combine for continuous, high performance required in today's demanding designs.
Bus-Friendly Inputs and I/Os
The MACH111 inputs and I/Os include two inverters in series which loop back to the input. This
double inversion reinforces the state of the input and pulls the voltage away from the input
threshold voltage. Unlike a pull-up, this configuration cannot cause contention on a bus. For an
illustration of this configuration, please turn to the Input/Output Equivalent Schematics section.
PCI Compliant
The MACH111-5/7/10/12 is fully compliant with the PCI Local Bus Specification published by
the PCI Special Interest Group. The MACH111-5/7/10/12’s predictable timing ensures
compliance with the PCI AC specifications independent of the design.
Power-Down Mode
The MACH111 features a programmable low-power mode in which individual signal paths can be
programmed as low power. These low-power speed paths will be slightly slower than the
non-low-power paths. This feature allows speed critical paths to run at maximum frequency while
the rest of the paths operate in the low-power mode, resulting in power savings of up to 50%.
Safe for Mixed Supply Voltage System Designs
The MACH111 is safe for mixed supply voltage system designs. The 5-V device will not overdrive
3.3-V devices above the output voltage of 3.3 V, while it accepts inputs from other 3.3-V devices.
Thus, the MACH111 provides easy-to-use mixed-voltage design compatibility.
MACH111-5/7/10/12/15
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