A42L0616S-50 AMICC [AMIC Technology], A42L0616S-50 Datasheet - Page 3

• Manufacturer Part Number: A42L0616S-50
• Description: 1M X 16 CMOS DYNAMIC RAM WITH EDO PAGE MODE
• Manufacturer: AMICC [AMIC Technology]

Selection Guide
Functional Description
The A42L0616 reads and writes data by multiplexing an
20-bit address into a 10-bit row and 10-bit column address.
column address, respectively.
The A42L0616 has two CAS inputs:
I/O
function in an identical manner to CAS in that either will
generate an internal CAS signal. The CAS function and
timing are determined by the first CAS (
Byte Read and Byte Write are controlled by using
and
A Read cycle is performed by holding the WE signal high
during RAS / CAS operation. A Write cycle is executed by
holding the WE signal low during RAS / CAS operation;
the input data is latched by the falling edge of WE or
are routed through 16 common I/O pins, with RAS , CAS ,
EDO Page Mode operation all 1024(1K) columns within a
selected row to be randomly accessed at a high data rate.
A EDO Page Mode cycle is initiated with a row address
latched by RAS followed by a column address latched by
strobe changing column addresses, thus achieving shorter
cycle times.
PRELIMINARY
RAS and CAS are used to strobe the row address and the
LCAS
CAS , whichever occurs later. The data inputs and outputs
CAS . While holding RAS low, CAS can be toggled to
WE and OE controlling the in direction.
7
Symbol
, and
UCAS
t
t
t
RAC
t
CAC
OEA
t
t
AA
RC
PC
) to transition low and by the last to transition high.
UCAS
separately.
Maximum RAS Access Time
Maximum Column Address Access Time
Maximum CAS Access Time
Maximum Output Enable ( OE ) Access Time
Minimum Read or Write Cycle Time
Minimum EDO Cycle Time
controls I/O
(June, 2002, Version 0.2)
8
- I/O
15
,
LCAS
UCAS
Description
controls I/O
and
UCAS
LCAS
LCAS
or
0
-
2
The A42L0616 offers an accelerated Fast Page Mode
cycle through a feature called Extended Data Out, which
keeps the output drivers on during the CAS precharge
time (t
the user is not required to wait for valid data to appear
before starting the next access cycle. Data-out will remain
valid as long as RAS and OE are low, and WE is high;
this is the only characteristic which differentiates Extended
Data Out operation from a standard Read or Fast Page
Read.
A memory cycle is terminated by returning both RAS and
maintaining
combinations of the 10-bit row addresses, regardless of
sequence, at least once every 16ms through any RAS
cycle (Read, Write) or RAS Refresh cycle ( RAS -only,
CBR, or Hidden). The CBR Refresh cycle automatically
controls the row addresses by invoking the refresh counter
and controller.
Power-On
The initial application of the VCC supply requires a 200 µs
wait followed by a minimum of any eight initialization cycles
containing a RAS clock. During Power-On, the VCC
current is dependent on the input levels of RAS and CAS .
It is recommended that RAS and CAS track with VCC or
be held at a valid V
surges.
CAS high. Memory cell data will retain its correct state by
cp
). Since data can be output after CAS goes high,
power
IH
-45
45
20
12
12
76
18
and
during Power-On to avoid current
AMIC Technology, Inc.
A42L0616 Series
accessing
-50
50
22
13
13
84
20
all
1024(1K)
Unit
ns
ns
ns
ns
ns
ns