ATA3742_07 ATMEL [ATMEL Corporation], ATA3742_07 Datasheet - Page 25

• Manufacturer Part Number: ATA3742_07
• Description: UHF ASK/FSK Receiver
• Manufacturer: ATMEL [ATMEL Corporation]

4900B–RKE–11/07
To start programming, the serial data line DATA is pulled to “L” for the time period t
microcontroller. When DATA has been released, the receiver becomes the master device. When
the programming delay period t
with the pulse length t
until the program window starts is determined by t
gramming window, the individual bits are set. If the microcontroller pulls down pin DATA for the
time period t
“1”. All 14 bits are subsequently programmed in this way. The time frame to program a bit is
defined by t
Bit 14 is followed by the equivalent time window t
edge pulse t
that was already stored in that register. E_Ack should be used to verify that the mode word was
correctly transferred to the register. The register must be programmed twice in that case.
Programming of a register is possible both during sleep and active mode of the receiver.
During programming, the LNA, LO, low-pass filter, IF amplifier and the FSK/ASK Manchester
demodulator are disabled.
The programming start pulse t
set to “1”, it represents the OFF command to set the receiver back to polling mode at the same
time. For the length of the programming start pulse t
considered:
Programming (or the OFF command) is initiated if the receiver is not in reset mode. If the
receiver is in reset mode, programming (or the OFF command) is not initiated, and the reset
marker (RM) is still present at pin DATA.
This period is generally used to switch the receiver to polling mode. In a reset condition, RM is
not canceled by accident.
Programming (or the OFF command) is initiated in any case. RM is canceled if present.
This period is used if the connected microcontroller detected RM. If a configuration register is
programmed, this time period for t
DATA is limited. The resulting time constant t together with an optional external pull-up resistor
may not be exceeded to ensure proper operation.
• t
• t
1
1
(min) < t
> 5632
6
8
7
.
1
(E_Ack) occurs if the just-programmed mode word is equivalent to the mode word
during t
< 1535
T
Clk
5
3
, the bit is set to “0”. If no programming pulse t
. After each of these pulses, a programming window occurs. The delay
T
Clk
: [t
1
1
(min) is the minimum specified value for the relevant BR_Range]
initiates the programming of the configuration registers. If bit 1 is
2
has elapsed, it emits 14 subsequent synchronization pulses
1
can generally be used. Note that the capacitive load at pin
9
4
. During this window, the equivalent acknowl-
, the duration is defined by t
1
, the following convention should be
7
is issued, this bit is set to
ATA3742
5
. Within the pro-
1
by the
25