ATA3742_07 ATMEL [ATMEL Corporation], ATA3742_07 Datasheet - Page 16
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ATA3742_07
Manufacturer Part Number
ATA3742_07
Description
UHF ASK/FSK Receiver
Manufacturer
ATMEL [ATMEL Corporation]
Datasheet
1.ATA3742_07.pdf
(34 pages)
Figure 5-4.
Figure 5-5.
Figure 5-6.
Figure 5-7.
16
ATA3742
(Lim_min = 14, Lim_max = 24)
Enable IC
Bit check
Bit check
Dem_out
counter
(Lim_min = 14, Lim_max = 24)
Enable IC
Bit check
(Lim_min = 14, Lim_max = 24)
Enable IC
Bit check
Bit check
Dem_out
counter
Timing Diagram for Complete Successful Bit Check
Timing Diagram During Bit Check
Timing Diagram for Failed Bit Check (Condition: CV_Lim < Lim_min)
Bit check
Dem_out
counter
Timing Diagram for Failed Bit Check (Condition: CV_Lim
(Number of checked Bits: 3)
Enable IC
Bit check
Dem_out
Data
Startup mode
Start up mode
Startup mode
T
Startup
0
0
0
1 2
1 2
1 2
3 4
3 4
3 4
T
5 6
XCLK
5 6
5 6
Bit check mode
7 8
1/2 Bit
1
7 1
2 3
1 2
2 3
4 5
1/2 Bit
3 4
1/2 Bit
4 5
6 7
5 6
Bit check mode
Bit check mode
6 7
8
1/2 Bit
7 8
Bit check failed (CV_Lim_ < Lim_min)
1/2 Bit
9 10
8
9 10
Bit check ok
9 10
1/2 Bit
11 12
1/2 Bit
11 12
11 12
13 14
13 14
1/2 Bit
15 16
Bit check ok
15 16
Lim_max)
17 18
17 18
Bit check failed (CV_Lim_
1/2 Bit
19 20
1 2
0
Sleep mode
21 22
3 4
23 24
5 6
1/2 Bit
Receiving mode
7 8
9 10
11 12
Sleep mode
Bit check ok
Lim_max)
0
13 14
15
1/2 Bit
1 2
3 4
4900B–RKE–11/07