K7N161801-FC13 SAMSUNG [Samsung semiconductor], K7N161801-FC13 Datasheet - Page 3

• Manufacturer Part Number: K7N161801-FC13
• Description: 512Kx36 & 1Mx18-Bit Flow Through NtRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

LOGIC BLOCK DIAGRAM
512Kx36 & 1Mx18-Bit Flow Through NtRAM
FEATURES
• 3.3V+0.165V/-0.165V Power Supply.
• I/O Supply Voltage 3.3V+0.165V/-0.165V for 3.3V I/O
• Byte Writable Function.
• Enable clock and suspend operation.
• Single READ/WRITE control pin.
• Self-Timed Write Cycle.
• Three Chip Enable for simple depth expansion with no data
• A interleaved burst or a linear burst mode.
• Asynchronous output enable control.
• Power Down mode.
• TTL-Level Three-State Outputs.
• 100-TQFP-1420A
• Operating in commeical and industrial temperature range.
FAST ACCESS TIMES
K7M163625A
K7M161825A
A [0:18]or
A [0:19]
CLK
CKE
CS
CS
CS
ADV
WE
BW
(x=a,b,c,d or a,b)
OE
ZZ
DQa
DQPa ~ DQPd
or 2.5V+0.4V/-0.125V for 2.5V I/O
Cycle Time
Clock Access Time
Output Enable Access Time
contention .
1
2
2
x
0
~ DQd
Parameter
7
or DQa
K
0
REGISTER
ADDRESS
~ DQb
Sym.
t
8
CYC
t
t
CD
OE
A
2
~A
-65
7.5
6.5
3.5
18
or A
LBO
A
2
0
~A
~A
-75
8.5
7.5
3.5
1
19
512Kx36 & 1Mx18 Flow-Through NtRAM
CONTROL
ADDRESS
COUNTER
REGISTER
ADDRESS
LOGIC
BURST
WRITE
NtRAM
Unit
ns
ns
ns
- 3 -
TM
and No Turnaround Random Access Memory are trademarks of Samsung.
GENERAL DESCRIPTION
The K7M163625A and K7M161825A are 18,874,368-bits Syn-
chronous Static SRAMs.
The NtRAM
lizes all bandwidth in any combination of operating cycles.
Address, data inputs, and all control signals except output
enable and linear burst order are synchronized to input clock.
Burst order control must be tied "High or Low".
Asynchronous inputs include the sleep mode enable(ZZ).
Output Enable controls the outputs at any given time.
Write cycles are internally self-timed and initiated by the rising
edge of the clock input. This feature eliminates complex off-chip
write pulse generation
and provides increased timing flexibility for incoming signals.
For read cycles, Flow-Through SRAM allows output data to
simply flow freely from the memory array.
The K7M163625A and K7M161825A are implemented with
SAMSUNG s high performance CMOS technology and is avail-
able in 100pin TQFP packages. Multiple power and ground pins
minimize ground bounce.
A
0
~A
TM
1
TM
, or No Turnaround Random Access Memory uti-
36 or 18
K
REGISTER
DATA-IN
512Kx36, 1Mx18
MEMORY
ARRAY
BUFFER
Nov. 2003
Rev 3.0
TM