K7R641884M SAMSUNG [Samsung semiconductor], K7R641884M Datasheet - Page 9

• Manufacturer Part Number: K7R641884M
• Description: 2Mx36 & 4Mx18 QDRTM II b4 SRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

K7R643684M
K7R641884M
ABSOLUTE MAXIMUM RATINGS*
*Note: 1. Stresses greater than those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating
OPERATING CONDITIONS
DC ELECTRICAL CHARACTERISTICS
Notes: 1. Minimum cycle. I
Input Leakage Current
Output Leakage Current
Operating Current (x36): DDR
Operating Current (x18): DDR
Standby Current(NOP): DDR
Output High Voltage
Output Low Voltage
Output High Voltage
Output Low Voltage
Input Low Voltage
Input High Voltage
Voltage on V
Voltage on V
Voltage on Input Pin Relative to V
Storage Temperature
Operating Temperature
Storage Temperature Range Under Bias
Supply Voltage
Reference Voltage
2. V
2. |I
3. Minimum Impedance Mode when ZQ pin is connected to V
4. Operating current is calculated with 50% read cycles and 50% write cycles.
5. Standby Current is only after all pending read and write burst opeactions are completed.
6. Programmable Impedance Mode.
7. These are DC test criteria. DC design criteria is V
8. V
9. V
only and functional operation of the device at these or any other conditions above those indicated in the operating sections of this specification
is not implied. Exposure to absolute maximum rating conditions for extended periods may affect reliability.
DDQ
timing parameters.
OH
IL
IH
PARAMETER
(Min)DC=
|=(V
(Max)DC=
must not exceed V
DD
DDQ
PARAMETER
DDQ
Supply Relative to V
Supply Relative to V
/2)/(RQ/5) 15% for 175
-
0.3V, V
V
DDQ
OUT
PARAMETER
+0.3, V
=0mA.
IL
DD
(Min)AC=-1.5V(pulse width
during normal operation.
IH
SS
(Max)AC=
SS
SYMBOL
SS
(0 C
V
V
V
V
I
I
I
V
I
V
SB1
I
CC
CC
OH1
OH2
OL
OL1
OL2
IL
IH
IL
RQ
V
DDQ
T
350 . |I
V
Output Disabled,
V
Cycle Time
V
Cycle Time
Device deselected,
I
All Inputs 0.2V or V
I
I
A
+0.85V(pulse width
OUT
OH
OL
DD
DD
DD
=1.0mA
=-1.0mA
REF
=Max ; V
=Max , I
=Max , I
70 C)
=0mA, f=Max,
SYMBOL
3ns).
(V
50mV. The AC V
V
V
OL
V
DDQ
TEST CONDITIONS
REF
DD
DD
|=(V
DDQ
OUT
OUT
=1.8V 0.1V, T
IN
DDQ
t
t
KHKH
KHKH
.
=V
- 9 -
=0mA
=0mA
/2)/(RQ/5) 15% for 175
SS
2Mx36 & 4Mx18 QDR
3ns).
Min
Min
to V
SYMBOL
DD
IH
/V
V
T
T
T
-0.2V
V
V
DDQ
DDQ
OPR
BIAS
STG
IL
DD
IN
levels are defined separately for measuring
A
=0 C to +70 C)
0.68
MIN
1.7
1.4
-30
-25
-20
-16
-30
-25
-20
-16
-30
-25
-20
-16
V
V
DDQ
DDQ
V
V
RQ
DDQ
REF
MIN
V
-0.3
-0.5 to V
-2
-2
/2-0.12 V
/2-0.12 V
-
-
-
-
-
-
-
-
-
-
-
-
SS
+0.1
-0.5 to V
350 .
-0.5 to 2.9
-65 to 150
-0.2
-10 to 85
RATING
0 to 70
MAX
0.95
1.9
1.9
DD+
DD
DDQ
DDQ
V
V
0.3
DDQ
REF
V
MAX
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TBD
TM
0.2
+2
+2
/2+0.12
/2+0.12
DDQ
+0.3
-0.1
Preliminary
II b4 SRAM
UNIT NOTES
mA
mA
mA
V
V
V
V
V
V
UNIT
A
A
UNIT
V
V
V
V
V
V
Oct. 2004
C
C
C
Rev 0.5
1,4
1,4
1,5
2,6
2,6
7,8
7,9
3
3