K7R641884M SAMSUNG [Samsung semiconductor], K7R641884M Datasheet - Page 4

• Manufacturer Part Number: K7R641884M
• Description: 2Mx36 & 4Mx18 QDRTM II b4 SRAM
• Manufacturer: SAMSUNG [Samsung semiconductor]

K7R643684M
K7R641884M
PIN CONFIGURATIONS
Notes: 1. * Checked No Connect(NC) pins are reserved for higher density address, i.e. 2A for 144Mb.
PIN NAME
Notes: 1. C, C, K or K cannot be set to V
BW
SYMBOL
A
B
C
D
G
H
K
M
N
R
CQ, CQ
E
F
L
P
J
D0-17
Q0-17
V
V
C, C
TMS
TCK
TDO
K, K
Doff
V
V
TDI
2. When ZQ pin is directly connected to V
NC
SA
0
ZQ
2. BW
3. Not connected to chip pad internally.
W
DDQ
REF
R
, BW
DD
SS
0
1
TDO
Doff
CQ
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
controls write to D0:D8 and BW
1
2A,10A,4C,8C,4D-8D,5E-7E,6F,6G,6H,6J,6K,5L-7L,4M-8M,4N,8N
3A,9A,10A,4B,8B,5C,7C,5N-7N,4P,5P,7P,8P,3R-5R,7R-9R
7A,1B,5B,9B,10B,1C,2C,6C,9C,1D,9D,10D,1E,2E,9E,1F
V
4E,8E,4F,8F,4G,8G,3H,4H,8H,9H,4J,8J,4K,8K,4L,8L
9F,10F,1G,9G,10G,1J,2J,9J,1K,2K,9K,1L,9L,10L,1M
SS
V
10P,11N,11M,10K,11J,11G,10E,11D,11C,3B,3C,2D
TCK
Q12
D13
Q15
D17
D11
11P,10M,11L,11K,10J,11F,11E,10C,11B,2B,3D,3E
NC
NC
NC
NC
NC
NC
Q9
REF
2
/SA*
5F,7F,5G,7G,5H,7H,5J,7J,5K,7K
(TOP VIEW) K7R641884M(4Mx18)
V
2M,9M,1N,9N,10N,1P,2P,9P
Q10
Q13
Q14
Q16
Q17
D10
Q11
D12
D14
D15
D16
SA
D9
SA
DDQ
REF
3
3F,2G,3J,3L,3M,2N
2F,3G,3K,2L,3N,3P
voltage.
PIN NUMBERS
1
DD
controls write to D9:D17.
output impedance is set to minimum value and it cannot be connected to ground or left unconnected.
11A, 1A
2H,10H
6B, 6A
7B, 5A
6P, 6R
V
V
V
V
V
V
V
V
V
V
V
SA
SA
SA
11H
10R
11R
W
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
1H
4A
8A
2R
1R
4
SS
SS
SS
SS
BW
V
V
V
V
V
V
V
V
V
NC
SA
SA
SA
SA
5
SS
SS
DD
DD
DD
DD
DD
SS
SS
1
- 4 -
2Mx36 & 4Mx18 QDR
V
V
V
V
V
V
V
V
V
NC
SA
K
K
C
C
6
SS
SS
SS
SS
SS
SS
SS
SS
SS
BW
V
V
V
V
V
V
V
V
V
NC
SA
SA
SA
SA
7
DD
DD
DD
DD
DD
SS
SS
SS
SS
0
Block Write Control Pin,active when low
Output Driver Impedance Control Input
Output Power Supply ( 1.5V or 1.8V )
Write Control Pin,active when low
Read Control Pin,active when low
Input Clock for Output Data
V
V
V
V
V
V
V
V
V
V
V
Input Reference Voltage
JTAG Test Mode Select
SA
SA
SA
JTAG Test Data Output
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
DDQ
Power Supply ( 1.8 V )
DLL Disable when low
R
8
JTAG Test Data Input
SS
SS
SS
SS
Output Echo Clock
JTAG Test Clock
DESCRIPTION
Address Inputs
Data Outputs
No Connect
Input Clock
Data Inputs
Ground
V
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
NC
SA
SA
DDQ
9
TM
Preliminary
II b4 SRAM
V
TMS
NC
NC
NC
NC
NC
NC
SA
Q7
Q4
Q1
D6
D3
D0
10
REF
Oct. 2004
Rev 0.5
TDI
NOTE
CQ
Q8
D8
D7
Q6
Q5
D5
ZQ
D4
Q3
Q2
D2
D1
Q0
11
1
2
3