K6R1008C1D SAMSUNG [Samsung semiconductor], K6R1008C1D Datasheet - Page 7
K6R1008C1D
Manufacturer Part Number
K6R1008C1D
Description
64Kx16 Bit High-Speed CMOS Static RAM(3.3V Operating) Operated at Commercial and Industrial Temperature Ranges.
Manufacturer
SAMSUNG [Samsung semiconductor]
Datasheet
1.K6R1008C1D.pdf
(11 pages)
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K6R1016V1D
TIMING WAVEFORM OF READ CYCLE(2)
Address
CS
UB, LB
OE
Data out
V
Current
TIMING WAVEFORM OF WRITE CYCLE(1)
CC
OE
Address
CS
UB, LB
WE
Data in
Data out
NOTES(READ CYCLE)
1. WE is high for read cycle.
2. All read cycle timing is referenced from the last valid address to the first transition address.
3. t
4. At any given temperature and voltage condition, t
5. Transition is measured 200mV from steady state voltage with Load(B). This parameter is sampled and not 100% tested.
6. Device is continuously selected with CS=V
7. For common I/O applications, minimization or elimination of bus contention conditions is necessary during read and write cycle.
V
device.
HZ
OL
I
I
and t
SB
levels.
CC
OHZ
High-Z
are defined as the time at which the outputs achieve the open circuit condition and are not referenced to V
High-Z
t
t
PU
t
BLZ(4,5)
LZ(4,5)
t
t
AS(4)
OLZ
(WE=V
50%
(OE =Clock)
t
AA
t
IL.
CO
IH
t
t
BA
OE
)
t
OHZ(6)
- 7 -
HZ
(Max.) is less than t
t
RC
t
t
AW
t
WC
CW(3)
t
BW
t
WP(2)
Valid Data
LZ
(Min.) both for a given device and from device to
t
DW
Valid Data
t
WR(5)
t
DH
50%
t
CMOS SRAM
PD
t
t
HZ(3,4,5)
BHZ(3,4,5)
t
t
DH
OHZ
for AT&T
High-Z
Revision 3.0
June 2002
OH
or