LV4904V SANYO [Sanyo Semicon Device], LV4904V Datasheet - Page 18

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LV4904V

Manufacturer Part Number
LV4904V
Description
Digital Input Class-D Power Amplifier
Manufacturer
SANYO [Sanyo Semicon Device]
Datasheet
8. Description of I
8.1 Input data settings
Figure 16.1.1 [DFORM_I
Figure 16.1.2 [DFORM _I
Figure 16.1.3 [DFORM _I
Figure 8.1.4 [DFORM_I
DFORM_I
The setting established according to DFORM_I
low in the combined I
established, the settings established according to the pins described in section 2.6 are valid, therefore DFORM_I
setting described here is ignored. Table 16.1.1 and Figure 16.1.1 to Figure 16.1.4 show the formats that are set by
DFORM_I
Table 8.1.1 Data format settings (initial setting in bold)
21
2
22
1
23
0
Register
23 22
DATA
2
2
23 22
C is set to match the format of the 3-wire serial input that is to be input.
C.
21 20
21 20
2
C Bus Registers
Address
DFORM_I
10h
2
C = 011/100/101/110] BCK=64 fs, 24/20/18/16 bits, right justified, MSB first
2
2
000
001
010
011
100
101
110
2
C = 0000] BCK=64 fs, I
C bus and pin setting mode. With any other pin settings or when the pin setting mode is
2
C = 0010] BCK=64 fs, right justified, LSB first (24 bits)
C = 0001] BCK=64 fs, left justified, MSB first (24 bits)
3
0
2
32fs
32fs
32fs
32fs
Lch
Lch
Lch
Lch
3
2
C
1
2
1
2
1
0
3
D7
0
0
24/20/18/16 bit
I
Left justified, MSB first
Right justified, LSB first
24 bits, right justified, MSB first
20 bits, right justified, MSB first
18 bits, right justified, MSB first
16 bits, right justified, MSB first
2
S
20
3
MCKFS_I
D6
21
2
22
2
1
C is valid only when the DFORM0, DFORM1, and DFORM2 pins are
2
S (24 bits)
23
0
LV4904V
23 22
2
C [1: 0]
Data Format
23 22
D5
21 20
21 20
D4
SRATE_I
3
0
32fs
32fs
32fs
32fs
Rch
Rch
Rch
Rch
3
2
1
1
2
2
2
1
0
C [1: 0]
3
0
24/20/18/16 bit
D3
20
3
21
2
D2
22
1
23
0
23 22
DFORM _I
23 22
21
21
20
D1
2
C [2: 0]
No.A1963-18/25
D0
2
C

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