SI8900-1 SILABS [Silicon Laboratories], SI8900-1 Datasheet

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SI8900-1

Manufacturer Part Number
SI8900-1
Description
ISOLATED MONITORING ADC
Manufacturer
SILABS [Silicon Laboratories]
Datasheet
I
Features
Applications
Description
The Si8900/1/2 series of isolated monitoring ADCs are useful as linear
signal galvanic isolators, level shifters, and/or ground loop eliminators in
many applications including power-delivery systems and solar inverters.
These devices integrate a 10-bit SAR ADC subsystem, supervisory state
machine and isolated UART (Si8900), I
Port (Si8902) in a single package. Based on Silicon Labs’ proprietary
CMOS isolation technology, ordering options include a choice of 2.5 or
5 kV isolation ratings. All products are safety certified by UL, CSA, and
VDE (pending). The Si8900/1/2 devices offer a typical common-mode
transient immunity performance of 45 kV/µs for robust performance in
noisy and high-voltage environments. Devices in this family are available
in 16-pin SOIC wide-body packages.
Safety Approval (Pending)
Rev. 1.0 6/12
SOLA TED
ADC



Isolated serial I/O port



Transient immunity:
45 kV/µs (typ)
Isolated data acquisition
AC mains monitor
Solar inverters
UL 1577 recognized

CSA component notice 5A
approval

Up to 5 kVrms for 1 minute
This information applies to a product under development. Its characteristics and specifications are subject to change without notice.
3 input channels
10-bit resolution
2 µs conversion time
UART (Si8900)
I
2.5 MHz SPI port (Si8902)
IEC 60950, 61010, 60601
2
C/SMbus (Si8901)
M
ONITORING
Copyright © 2012 by Silicon Laboratories
Temperature range:
–40 to +85 °C
>60-year life at rated working
voltage
CSA component notice 5A
approval
IEC 60950, 61010, 60601
VDE/IEC 60747-5-2
UL1577 recognized

Isolated temp/humidity sensing
Switch mode power systems
Telemetry
VDE certification conformity
IED 60747-5-2 (VDE 0884 Part 2)
2
C/SMbus port (Si8901), or SPI
Up to 5 kVrms for 1 minute
ADC
GNDA
GNDA
GNDA
VDDA
VDDA
RSDA
VDDA
S i 8 9 0 0 / 1 / 2
VREF
VREF
VREF
RST
AIN0
AIN1
AIN2
AIN0
AIN1
AIN2
AIN0
AIN1
AIN2
RST
RST
NC
NC
Ordering Information:
Pin Assignments
See page 25.
Si8901
Si8902
Si8900
Si8900/1/2
VDDB
NC
NC
SCL
SDA
NC
VDDB
GNDB
VDDB
NC
SDO
SCLK
SDI
EN
VDDB
GNDB
VDDB
NC
NC
Rx
Tx
NC
VDDB
GNDB

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SI8900-1 Summary of contents

Page 1

... AC mains monitor  Solar inverters Description The Si8900/1/2 series of isolated monitoring ADCs are useful as linear signal galvanic isolators, level shifters, and/or ground loop eliminators in many applications including power-delivery systems and solar inverters. These devices integrate a 10-bit SAR ADC subsystem, supervisory state machine and isolated UART (Si8900), I Port (Si8902 single package. Based on Silicon Labs’ ...

Page 2

... Si8900/1/2 2 Rev. 1.0 ...

Page 3

... Regulatory Information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .9 3. Functional Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 4. ADC Data Transmission Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 11 4.1. UART (Si8900 4.2. I2C/SMBus (Si8901 .14 4.3. SPI Port (Si8902 4.4. Master Controller Firmware . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 5. Si8900/1/2 Configuration Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6. Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 6.1. Isolated Outputs . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 6.2. Device Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 6.3. Application Example . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 7. Device Pin Assignments . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 8. Ordering Guide . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 9. Package Outline: 16-Pin Wide Body SOIC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 10 ...

Page 4

... Si8900/1/2 1. Electrical Specifications Table 1. Recommended Operating Conditions Parameter Symbol Input Side Supply Voltage V DDA Input Side Supply Current I DDA Output Side Supply Voltage V DDB Output Side Supply Current I DDB Operating Temperature T A Table 2. Electrical Specifications Parameter Symbol ADC Resolution Integral Nonlinearity ...

Page 5

... V, OH DDB I = – 3.3 V, DDB I = – 3 DDB OUT Slave Address = 1111000x Rev. 1.0 Si8900/1/2 Min Typ Max Units — — 1.8 1.7 — — — — 1 0.3 — 2.3 — — 100 — — — DDB — — ...

Page 6

... Si8900/1/2 Table 2. Electrical Specifications (Continued) Parameter Symbol SPI Port Timing EN Falling Edge to SCLK Rising Edge Last Clock Edge to /EN Rising EN Falling to SDO Valid EN Rising to SDO High-Z SCLK High Time SCLK Low Time SDI Valid to SCLK Sample Edge SCLK Sample Edge to SDI ...

Page 7

... DD2 370 3.6 V DD1 DD2 220 5.5 V DD1 DD2 0 50 100 150 Temperature (ºC) 430 2.70 V DD1 DD2 360 3.6 V DD1 DD2 210 5.5 V DD1 DD2 0 50 100 150 Temperature (ºC) Rev. 1.0 Si8900/1/2 WB SOIC-16 NB SOIC-16 Unit 100 105 ºC/W 200 200 7 ...

Page 8

... Si8900/1/2 Table 4. Absolute Maximum Ratings Parameter Storage Temperature Ambient Temperature under Bias Input-Side Supply Voltage Output-Side Supply Voltage Input/Output Voltage Output Current Drive Lead Solder Temperature (10 s) Maximum Isolation Voltage *Note: Permanent device damage may occur if the absolute maximum ratings are exceeded. Functional operation should be restricted to conditions as specified in the operational sections of this data sheet ...

Page 9

... Regulatory Information The Si8900/1/2 family is certified by Underwriters Laboratories, CSA International, and VDE. Table 5 summarizes the certification levels supported. CSA The Si89xx is certified under CSA Component Acceptance Notice 5A. For more details, see File 232873. 61010- 600 VRMS reinforced insulation working voltage 600 VRMS basic insulation working voltage. ...

Page 10

... ADC conversion data by reading the Si890x serial port. Devices in this series differ only in the type of serial port. Options include a UART with on-chip baud rate generator that operates at 234 kbps max (Si8900), an SMBus/I port that operates at 240 kbps max (Si8901), and an SPI Port that operates at 2.5 MHz max (Si8902). ...

Page 11

... C/SMBus Slave Address byte (Si8901 Slave Address is 0xF0). The Si8902 Demand Mode ADC read transaction (Figure 5C) is the same as that of the Si8900, except the master must wait 8 µs after the transmission of the Command Byte before reading the Si8902 SPI port because byte transmission time is two times shorter versus the Si8900/01 ...

Page 12

... The Burst Mode ADC transactions for the Si8900 (Figure 6A) and Si8901 (Figure 6B) are substantially the same. A Burst Mode ADC read is initiated when the master writes a CNFG_0 (MODE = 0) Command Byte to the Si8900/1, which updates the CNFG_0 register and triggers the ADC continuously. Like the Demand Mode example, the Si8901 has a Slave Address byte prior to the CNFG_0 Command Byte ...

Page 13

... There are a total of 10 bits per data read/write: One start bit, eight data bits (LSB first), and one stop bit with data transmitted LSB first as shown in Figure 7. Figure 8A and Figure 8B show master/Si8900 ADC read transactions for Demand Mode and Burst Mode, respectively. ...

Page 14

... Si8900/1/2 2 4.2. I C/SMBus (Si8901) 2 The I C/SMBus serial port is a two-wire serial bus where data line SDA is bidirectional and clock line SCL is unidirectional. Reads and writes to this interface by the master are byte-oriented, with the I controlling the serial data rates up to 240 kbps. The SDA and SCL lines must be pulled high through pull-up resistors of 5 k ...

Page 15

... D7  D6  D5   D4   D3  D2   D1   D0 Si8901 Read  Si8901 CNFG_0  Slave Address Read Data SDI SDO /EN SCLK Rev. 1.0 Si8900/1/2 ADC Data D7  D6   D5  D4   D3  D2   D1  D0 D7  ...

Page 16

... Si8900/1/2 4.3. SPI Port (Si8902) EN SCLK SDI MSB Bit 6 SDO MSB Bit 6 The Serial Peripheral Interface (SPI port slave mode, full-duplex, synchronous, 4-wire serial bus that connects to the master as shown in Figure 12. The master's clock and data timing must match the Si8902 timing shown Figure 12 (for more information about clock and data timing, please see the “ ...

Page 17

... Periodic ADC Data C)  Si8902 ADC Burst Mode Read Rev. 1.0 Si8900/1 D7  D6   D5   D4   D3   D2   D1   D0 ADC Data ...

Page 18

... Si8900/1/2 5. Si8900/1/2 Configuration Registers CNFG_0 Command Byte Bit D7 D6 Name 1 1 Type R/W R/W Default 1 1 Bit Name 7:6 1,1 Internal use. These bits are always set to 1. 5:4 MX1, MX0 ADC MUX Address. ADC MUX address selection is controlled by MX1, MX0 as follows: MX1 VREF ADC Voltage Reference Source VDD is selected as the reference voltage when this bit is set to 1 ...

Page 19

... Internal use. This bit is always set MX1 MX0 — — — Function — — — Function Rev. 1.0 Si8900/1 — — — — — — 19 ...

Page 20

... Si8900/1/2 6. Applications 6.1. Isolated Outputs The Si890x serial outputs are internally isolated from the device input side. To ensure safety in the end-user application, high voltage circuits (i.e., circuits with >30 VAC) must be physically separated from the safety extra-low voltage circuits (i.e., circuits with <30 VAC certain distance (creepage/clearance component straddles this isolation barrier, it must meet those creepage/clearance requirements and also provide a sufficiently large high-voltage breakdown protection rating (commonly referred to as working voltage protection) ...

Page 21

... RST input low k pull-up resistor on RST is recommended to avoid erroneous reset events from external noise coupling to the RST input. V RSTH V RSTL V (min) DDA Internal  RESET Power‐On Reset Figure 16. Si890x Power-on and Monitor Reset V DDA tPOR VDDA  Monitor  Reset Rev. 1.0 Si8900/1/2 21 ...

Page 22

... Si8900/1/2 6.3. Application Example Figure 17 shows the Si8900 operating as a single-phase ac line voltage and current monitor. The VDDA dc bias circuit uses a low-cost 3.3 V linear regulator referenced to the neutral (white wire). The ac current is measured on ADC input AIN0. The ac line voltage is scaled by resistors R17 and R18 and level-shifted by the 1.5 V VREF. AC line current is measured using differential amplifier U1 connected across shunt resistor R1 ...

Page 23

... Figure 18. Si8900/1/2 Pinout (16SOW) Table 6. Si8900/1/2 Pin Assignments Pin Si8900 Si8901 Si8902 Pin Pin Pin 1 VDDA 2 VREF RST 3 AIN0 AIN0 NC 4 AIN1 AIN1 VREF Si8900: ADC analog input channel 1. 5 AIN2 AIN2 AIN0 6 NC RST AIN1 7 RST RSDA AIN2 8 GNDA 9 GNDB 10 VDDB 11 NC ...

Page 24

... Si8900/1/2 Table 6. Si8900/1/2 Pin Assignments (Continued) Pin Si8900 Si8901 Si8902 Pin Pin Pin 14 NC SDO VDDB 24 Description Si8900/1: No connection. Si8902: SPI port Serial data out (SDO) No connection Si8900/1/2: Output side VDD bias voltage (2 5.5 V). Rev. 1.0 ...

Page 25

... Si8902D-A01-GS SPI Port Notes: 1. Add an “R” suffix to the part number to specify the tape and reel option. Example: “Si8900AB-A-ISR”. 2. All packages are RoHS-compliant. 3. Moisture sensitivity level is MSL3 for wide-body SOIC-16 package with peak reflow temperatures of 260 °C according to the JEDEC industry standard classifications and peak solder temperatures. ...

Page 26

... Si8900/1/2 9. Package Outline: 16-Pin Wide Body SOIC Figure 19 illustrates the package details for the Si8900/1/2 Digital Isolator. Table 8 lists the values for the dimensions shown in the illustration. Table 8. Package Diagram Dimensions 26 Figure 19. 16-Pin Wide Body SOIC Millimeters Symbol Min Max A — ...

Page 27

... Land Pattern: 16-Pin Wide-Body SOIC Figure 20 illustrates the recommended land pattern details for the Si8900/1 16-pin wide-body SOIC. Table 9 lists the values for the dimensions shown in the illustration. Table 9. 16-Pin Wide Body SOIC Land Pattern Dimensions Dimension Notes: 1 ...

Page 28

... Si8900/1/2 11. Top Marking: 16-Pin Wide Body SOIC 11.1. Si8900/1/2 Top Marking 11.2. Top Marking Explanation Base Part Number Ordering Options Line 1 Marking: (See Ordering Guide for more information Year WW = Workweek Line 2 Marking: TTTTTT = Mfg Code Circle = 1.5 mm Diameter (Center-Justified) Line 3 Marking: Country of Origin ISO Code ...

Page 29

... OCUMENT HANGE IST Revision 0.5 to Revision 1.0  No changes. : Rev. 1.0 Si8900/1/2 29 ...

Page 30

... Si8900/1 ONTACT NFORMATION Silicon Laboratories Inc. 400 West Cesar Chavez Austin, TX 78701 Tel: 1+(512) 416-8500 Fax: 1+(512) 416-9669 Toll Free: 1+(877) 444-3032 Please visit the Silicon Labs Technical Support web page: https://www.silabs.com/support/pages/contacttechnicalsupport.aspx and register to submit a technical support request. The information in this document is believed to be accurate in all respects at the time of publication but is subject to change without notice. ...

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