LUCW3000CCN AGERE [Agere Systems], LUCW3000CCN Datasheet - Page 15

• Manufacturer Part Number: LUCW3000CCN
• Description: W3000 PLL Dual-Band Frequency Synthesizer
• Manufacturer: AGERE [Agere Systems]

Advance Data Sheet
December 1999
MAIN Register
The MAIN register is intended for programming that can occur frequently for dynamic channel switching and
putting the W3000 into power-saving mode.
Table 18. MAIN Register Bit Description (C0 = 0, C1 = 0)
Table 19. MAIN Register
Note: X bits are don’t care bits.
Table 20. A1:A7: Swallow Counter Count (Bits 2 to 8)
= 0
C0
1
Bit 8
9:19
Lucent Technologies Inc.
Bit
2:8
A7
20
21
22
23
24
0
0
0
0
1
1
.
.
.
.
.
.
A
2
1
Last bit in serial sequence
3
A
2
4
A
3
Bit 7
Reserved
Reserved
A6
0
0
0
1
1
M[1:11]
.
.
.
.
.
.
C0 = 0
C1 = 0
Name
A[1:7]
A
5
4
EN2
B
A
6
5
A
7
6
Bit 6
A5
0
0
0
1
1
.
.
.
.
.
.
A
8
7
Register address bit. C0 = 0 for MAIN (last bit in serial sequence).
Swallow counter for prescaler modulus control.
Main counter.
Enable all PLL circuits (0 = powerdown mode).
Band select for charge pump current control (band 1 = 0, band 2 = 1).
Secondary address bit.
M
9
1
Bit 5
10
M
2
A4
0
0
0
1
1
.
.
.
.
.
.
11
M
3
12
M
4
Bit 4
A3
0
0
0
1
1
W3000 PLL Dual-Band Frequency Synthesizer
.
.
.
.
.
.
13
M
5
14
M
6
Bit 3
15
M
A2
7
Description
0
0
1
1
1
.
.
.
.
.
.
16
M
8
—
—
17
M
9
Bit 2
A1
0
1
0
1
1
.
.
.
.
.
.
First bit in serial sequence
18
10
M
19
11
M
Counter Ratio
20
X
127
63
0
1
2
.
.
.
.
.
.
21
X
EN
22
23
B
= 0
C1
24
15