HS-3282_02 INTERSIL [Intersil Corporation], HS-3282_02 Datasheet
HS-3282_02
Related parts for HS-3282_02
HS-3282_02 Summary of contents
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... The timing circuit is used to correctly separate each ARINC word as required by ARINC Specification 429. Even though ARINC Specification 429 specifies a 32-bit word, including parity, the HS-3282 can be programmed to also operate with a word length of 25 bits. The incoming receiver data word parity is checked, and a parity status is stored in the receiver latch and output on Pin BD08 during the 1st word ...
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... PL1 BD12 14 27 BD00 BD11 15 26 BD01 BD10 16 25 BD02 BD09 17 24 BD03 BD08 18 23 BD04 BD07 19 22 BD05 BD06 20 21 GND HS-3282 (CLCC) TOP VIEW ...
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... Transmitter 29 PL2 Transmitter 30 TX/R Transmitter HS-3282 DESCRIPTION Supply pin 5 volts ±5%. ARlNC 429 data input to Receiver 1. ARlNC 429 data input to Receiver 1. ARINC 429 data input to Receiver 2. ARINC 429 data input to Receiver 2. Device ready flag output from Receiver 1 indicating a valid data word is ready to be fetched. ...
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... Pinout HS-3282 DESCRIPTION Data output from Transmitter Data output from Transmitter. Transmitter Enable input signal to initiate data transmission from FIFO memory. Control word input strobe signal to latch the control word from the databus into the control word register. ...
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... LSl circuit. It goes beyond the ARlNC requirements by providing for either odd or even parity, and giving the user a choice of either 25 or 32-bit word lengths. The receiver and transmitter sections operate independently of each other. The serial-to- parallel conversion required of the receiver and the parallel- to-serial conversion requirements of the transmitter have been incorporated into the bus interface circuit ...
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... The receiver consists of the following circuits: HS-3282 • The Line Receiver functions as a voltage level translator. It transforms the 10 volt differential line voltage, ARINC 429 format, into 5 volt internal logic level. ...
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... PARCK set to a logic “0” will result in odd parity and when set to a logic “1” will result in even parity. HS-3282 Sample Interface Technique From Figure 1, one can see that the Data Bus is time shared between the Receiver and Transmitter ...
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... LINE RECEIV. 429D12 ( SEL SELF TEST WLSEL RCV CLK D/R1 D/R2 FIGURE 1. SINGLE CHIP ARINC 429 INTERFACE FUNCTIONAL BLOCK DIAGRAM HS-3282 CLK 37 RCV CLK RCV TX RCVSEL WDCNT 1 WORD GAP TIMING TXSEL DATA CLOCK DATA S/R 1 RCV TX CLK CLK 32 LATCH 1 ...
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... Operating Conditions Operating Voltage Range . . . . . . . . . . . . . . . . . . . +4.75V to +5.25V Operating Temperature Range HS-3282- HS-3282- -55 CAUTION: Stresses above those listed in “Absolute Maximum Ratings” may cause permanent damage to the device. This is a stress only rating and operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. ...
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... Output Data Bit Time 1/ Output Data Bit Time 2/ Output Data Null Time 1/ Output Data Null Time 2/ HS-3282 ±5 +70 C (HS-3282-5 - +125 C (HS-3282-8) A SYMBOL CONDITIONS 4.75V, 5.25V 4.75V, 5.25V 4.75V, 5.25V DD TMR V = 4.75V, 5.25V ...
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... Open 1MHz, Note Open 1MHz, Note Open 1MHz, Note CLK = 1MHz, From 0.7V to 3.5V CLK = 1MHz, From 3.5V to 0.7V From 0.7V to 3.5V, Note 6 From 3.5V to 0.7V, Note 6 193 o C (HS-3282-5 (HS-3282-8) (Continued) LIMITS MIN MAX UNITS µs 39.6 40.4 µs 316.8 323.2 - 400 ...
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... EN1 EN2 SEL TIME INTERVAL A BUS IS BEING USED AS AN OUTPUT FIGURE 2. TYPICAL INTERFACE TIMING SEQUENCE 429DI BIT 32 t D/R D/R EN SEL BD00-15 SEL BD00-15 HS-3282 TIME TIME INTERVAL B INTERVAL C INTERVAL D BUS IS BEING USED AS AN INPUT t END D/REN ENEN t SELEN t t SELEN ENSEL ...
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... Timing Waveforms (Continued) CWSTR BD00-15 PL1 t PL PL2 TX/R t DWSET BD00-15 WORD 1 TX/R ENTX t ENDAT BIT 42900 1 HS-3282 t CWSTR t CWHLD t CWSET CONTROL WORD FIGURE 4. CONTROL WORD TIMING t PL12 DWSET t DWHLD WORD 2 FIGURE 5. TRANSMITTER FIFO WRITE TIMING t BIT t t NUL NUL t GAP BIT ...
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... Timing Waveforms (Continued) 429DI BIT 32 t D/R D/R t D/REN EN t SELEN SEL t ENPL PL1 PL2 TX/R ENTX 429D0 HS-3282 t END/R t ENEN SELEN t t ENSEL ENSEL t PLEN t ENPL t PLEN t TX/R t TX/REN t ENDAT BIT 1 FIGURE 7. REPEATER OPERATION TIMING 196 t ENTX/R t NUL BIT 32 t DTX/R ...
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... However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com HS-3282 HS-3282 CERDIP ...
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... Burn-In Circuits F15 F14 F13 F12 F11 NOTES: 1. Resistors = 47kΩ, 5%, 1/4W (Min) 2. GND = Ground = +5.5V, ±0. 0.01mF/Socket (Min 100kHz F0/ F15 = F14/2 HS-3282 CLCC GND D/ D/R2 37 CWSTR 10 ENTX ...
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... No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries. For information regarding Intersil Corporation and its products, see www.intersil.com GLASSIVATION: Type: SiO 2 Thickness: 8kA ±1k Å WORST CASE CURRENT DENSITY A/cm HS-3282 (36) N/C (35) N/C (34) CWSTR (33) ENTX (32) 429D0 (31) 429D0 (30) TX/R (29) PL2 (28) PL1 (27) BD00 199 ...