ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 6

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Programmable FPGA Features
Programmable Logic System Features
6 6
Built-in testability:
— Full boundary scan (IEEE 1149.1 and Draft
— Programming and readback through boundary
— TS_ALL testability function to 3-state all I/O pins.
— New temperature-sensing diode.
New cycle stealing capability allows a typical 15% to
40% internal speed improvement after final place
and route. This feature also enables compliance with
many setup/hold and clock to out I/O specifications
and may provide reduced ground bounce for output
buses by allowing flexible delays of switching output
buffers.
PCI local bus compliant for FPGA I/Os.
Improved PowerPC
synchronous microprocessor interface can be used
for configuration, readback, device control, and
device status, as well as for a general-purpose inter-
face to the FPGA logic, RAMs, and embedded back-
plane transceiver blocks. Glueless interface to
synchronous PowerPC processors with user-config-
urable address space provided.
New embedded AMBA
tem bus (ARM
tion among the microprocessor interface,
configuration logic, embedded block RAM, FPGA
logic, and backplane transceiver logic.
New network PLLs meet ITU-T G.811 specifications
and provide clock conditioning for DS-1/E-1 and
STS-3/STM-1 applications.
Flexible general-purpose PPLLs offer clock multiply
(up to 8x), divide (down to 1/8x), phase shift, delay
compensation, and duty cycle adjustment combined.
1149.2 JTAG).
scan port compliant to IEEE Draft 1532:D1.7.
®
processor) facilitates communica-
®
860 and PowerPC II high-speed
™
specification 2.0 AHB sys-
(continued)
Variable size bused readback of configuration data
capability with the built-in microprocessor interface
and system bus.
Internal, 3-state, and bidirectional buses with simple
control provided by the SLIC.
New clock routing structures for global and local
clocking significantly increases speed and reduces
skew (<200 ps for OR4E4).
New local clock routing structures allow creation of
localized clock trees.
New edge clock routing supports at least six fast
edge clocks per side of the device
New double-data rate (DDR) and zero-bus turn-
around (ZBT) memory interfaces support the latest
high-speed memory interfaces.
New 2x/4x uplink and downlink I/O capabilities inter-
face high-speed external I/Os to reduced speed
internal logic.
ORCA Foundry 2000 development system software.
Supported by industry-standard CAE tools for design
entry, synthesis, simulation, and timing analysis.
Meets universal test and operations PHY interface
for ATM (UTOPIA) Levels 1, 2, and 3. Also meets
proposed specifications for UTOPIA Level 4 for
10 Gbits/s interfaces.
Two new edge clock routing structures allow up to
seven high-speed clocks on each edge of the device
for improved setup/hold and clock to out perfor-
mance.
Agere Systems Inc.
August 2001
Data Sheet