ORT8850H AGERE [Agere Systems], ORT8850H Datasheet - Page 2

• Manufacturer Part Number: ORT8850H
• Description: Field-Programmable System Chip (FPSC) Eight-Channel x 850 Mbits/s Backplane Transceiver
• Manufacturer: AGERE [Agere Systems]

Contents
ORCA ORT8850 FPSC
Eight-Channel x 850 Mbits/s Backplane Transceiver
Introduction..................................................................1
Embedded Core Features (Serial)...............................4
Embedded Core Features (Parallel)............................4
Programmable FPGA Features ...................................5
Programmable Logic System Features .......................6
Description...................................................................7
System-Level Features..............................................10
ORT8850 Overview ...................................................12
Generic Backplane Transceiver Application..............17
Backplane Transceiver Core Detailed Description ....18
2
What Is an FPSC? ...................................................7
FPSC Overview .......................................................7
FPSC Gate Counting ...............................................7
FPGA/Embedded Core Interface .............................7
ORCA Foundry Development System .....................7
FPSC Design Kit ......................................................8
FPGA Logic Overview ..............................................8
PLC Logic ................................................................8
Programmable I/O ....................................................9
Routing .....................................................................9
Microprocessor Interface .......................................10
System Bus ............................................................10
Phase-Locked Loops .............................................10
Embedded Block RAM ...........................................10
Configuration ..........................................................11
Additional Information ............................................11
Device Layout ........................................................12
Backplane Transceiver Interface ...........................12
HSI Interface ..........................................................15
STM Macrocell .......................................................15
8B/10B Encoder/Decoder ......................................15
FPGA Interface ......................................................15
Byte-Wide Parallel Interface ..................................15
FPSC Configuration ...............................................16
Synchronous Transfer Mode (STM) .......................17
8B/10B Mode .........................................................17
HSI Macro ..............................................................18
STM Transmitter (FPGA Æ Backplane) .................20
STM Receiver (Backplane Æ FPGA) .....................23
8B/10B Transmitter (FPGA Æ Backplane) ............30
8B/10B Receiver (Backplane Æ FPGA) ................30
Pointer Mover Block (Backplane Æ FPGA) ...........31
Receive Bypass Options and FPGA Interface .......33
Table of Contents
Page
Contents
RapidIO Interface to Pi-Sched.................................. 34
Memory Map............................................................. 38
Absolute Maximum Ratings...................................... 55
Recommended Operating Conditions ...................... 55
Power Supply Decoupling LC Circuit........................ 56
HSI Electrical and Timing Characteristics ................ 57
Parallel RapidIO -like Interface Timing
Embedded Core LVDS I/O ....................................... 59
Input/Output Buffer Measurement Conditions
LVDS Buffer Characteristics..................................... 62
Pin Information ......................................................... 63
Package Thermal Characteristics Summary .......... 105
Package Thermal Characteristics........................... 106
Package Coplanarity .............................................. 106
Package Parasitics ................................................. 106
Package Outline Diagrams..................................... 107
Package Outline Drawings ..................................... 108
Hardware Ordering Information .............................. 110
Software Ordering Information ............................... 111
Characteristics......................................................... 58
(on-LVDS Buffer)..................................................... 61
Powerdown Mode ................................................. 33
STM Redundancy and Protection Switching ......... 33
LVDS Protection Switching ................................... 34
Overview ............................................................... 34
Receive Cell Interface ........................................... 34
Transmit Cell Interface .......................................... 36
Definition of Register Types .................................. 38
LVDS Receiver Buffer Requirements .................... 60
Termination Resistor ............................................. 62
LVDS Driver Buffer Capabilities ............................ 62
Package Pinouts ................................................... 77
FPSC Maximum Junction Temperature .............. 105
Terms and Definitions ......................................... 107
352-Pin PBGA ..................................................... 108
680-Pin PBGAM .................................................. 109
JA ..................................................................... 105
JC ..................................................................... 105
JB ..................................................................... 105
JC ..................................................................... 105
Agere Systems Inc.
August 2001
Data Sheet
Page