ORT82G5-1BM680C LATTICE [Lattice Semiconductor], ORT82G5-1BM680C Datasheet - Page 63
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ORT82G5-1BM680C
Manufacturer Part Number
ORT82G5-1BM680C
Description
0.6 to 3.7 Gbps XAUI and FC FPSCs
Manufacturer
LATTICE [Lattice Semiconductor]
Datasheet
1.ORT82G5-1BM680C.pdf
(119 pages)
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Lattice Semiconductor
Table 28. ORT42G5 Memory Map (Continued)
Control Registers (Read/Write), xx=[AC, AD, BC or BD]
30800 - Ax
30900 - Bx
30801 - Ax
30901 - Bx
Absolute
Address
(0x)
Bit
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
[0]
[1]
[2]
[3]
[4]
[5]
[6]
[7]
ENBYSYNC_xC
LCKREFN_xC
LCKREFN_xD
LOOPENB_xC
LOOPENB_xD
NOWDALIGN_xC
NOWDALIGN_xD
ENBYSYNC_xD
Name
—
—
—
—
—
—
—
—
Reset
Value
(0x)
00
00
ENBYSYNC_xC= 1 Enables Receiver Byte Synchronization for Channel
xC. ENBYSYNC_xC = 0 on device reset.
ENBYSYNC_xD = 1 Enables Receiver Byte Synchronization for Channel
xA. ENBYSYNC_xD = 0 on device reset.
LCKREFN_xC = 0 Locks the receiver PLL to reference clock for Channel
xC.
LCKREFN_xC =1 = Locks the receiver to data for Channel xx.
NOTE: When LCKREFN_xx = 0, the corresponding LKI_xx bit is also 0.
LCKREFN_xC = 0 on device reset.
LCKREFN_xD = 0 Locks the receiver PLL to reference clock for Channel
xD.
LCKREFN_xD =1 = Locks the receiver to data for Channel xA.
NOTE: When LCKREFN_xx = 0, the corresponding LKI_xx bit is also 0.
LCKREFN_xD = 0 on device reset.
Enable Loopback Mode for Channel xC. When LOOPEN_xC=1, the
transmitter high-speed output is looped back to the receiver high-speed
input. This mode is similar to high-speed loopback mode enabled by
TESTMODE_xx except that LOOPEN_xx disables the high-speed serial
output. LOOPEN_xC=0 on device reset.
Enable Loopback Mode for Channel xD. When LOOPEN_xD=1, the
transmitter high-speed output is looped back to the receiver high-speed
input. This mode is similar to high-speed loopback mode enabled by
TESTMODE_xx except that LOOPEN_xx disables the high-speed serial
output. LOOPEN_xD=0 on device reset.
Word Align Disable Bit. When NOWDALIGN_xC=1, receiver word align-
ment is disabled for Channel xC. NOWDALIGN_xC=0 on device reset.
Word Align Disable Bit. When NOWDALIGN_xD=1, receiver word align-
ment is disabled for Channel xD. NOWDALIGN_xD=0 on device reset.
63
ORCA ORT42G5 and ORT82G5 Data Sheet
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
Reserved for future use
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Reserved for future use
Reserved for future use
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