EDD51321DBH-5BTS-F ELPIDA [Elpida Memory], EDD51321DBH-5BTS-F Datasheet
EDD51321DBH-5BTS-F
Manufacturer Part Number
EDD51321DBH-5BTS-F
Description
Manufacturer
ELPIDA [Elpida Memory]
Datasheet
1.EDD51321DBH-5BTS-F.pdf
(58 pages)
Specifications
Document No. E1398E40 (Ver. 4.0)
Date Published October 2009 (K) Japan
Printed in Japan
URL: http://www.elpida.com
Density: 512M bits
Organization: 4M words
Package: 90-ball FBGA
Power supply: VDD, VDDQ
Data rate: 400Mbps/333Mbps (max.)
2KB page size
Four internal banks for concurrent operation
Interface: LVCMOS
Burst lengths (BL): 2, 4, 8
Burst type (BT):
/CAS Latency (CL): 3
Precharge: auto precharge option for each burst
access
Driver strength: normal, 1/2, 1/4
Refresh: auto-refresh, self-refresh
Refresh cycles: 8192 cycles/64ms
Operating ambient temperature range
Lead-free (RoHS compliant) and Halogen-free
Row address: A0 to A12
Column address: A0 to A8
Sequential (2, 4, 8)
Interleave (2, 4, 8)
Average refresh period: 7.8 s
TA = 25 C to +85 C
EDD51321DBH-TS (16M words 32 bits)
512M bits DDR Mobile RAM
WTR (Wide Temperature Range)
32 bits
1.7V to 1.95V
PRELIMINARY DATA SHEET
4 banks
Features
DLL is not implemented
Low power consumption
Double-data-rate architecture; two data transfers per
one clock cycle
The high-speed data transfer is realized by the 2 bits
prefetch pipelined architecture
Bi-directional data strobe (DQS) is transmitted
/received with data for capturing data at the receiver.
Data inputs, outputs, and DM are synchronized with
DQS
DQS is edge-aligned with data for READs; center-
aligned with data for WRITEs
Differential clock inputs (CK and /CK)
Commands entered on each positive CK edge: data
and data mask referenced to both edges of DQS
Data mask (DM) for write data
Burst termination by burst stop command and
Precharge command
Wide temperature range
Low Power Function below is not supported
TA = 25 C to +85 C
Partal Array Self-Refresh (PASR)
Auto Temperature Compensated Self-Refresh
Deep power-down mode
Elpida Memory, Inc. 2008-2009
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