CYUSB3011-BZXC CYPRESS [Cypress Semiconductor], CYUSB3011-BZXC Datasheet - Page 24

• Manufacturer Part Number: CYUSB3011-BZXC
• Manufacturer: CYPRESS [Cypress Semiconductor]

Slave FIFO Interface
Synchronous Slave FIFO Sequence Description
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Document Number: 001-52136 Rev. *L
FIFO address is stable and SLCS is asserted
SLOE is asserted. SLOE is an output-enable only, whose sole
function is to drive the data bus.
SLRD is asserted
The FIFO pointer is updated on the rising edge of the PCLK,
while the SLRD is asserted. This starts the propagation of data
from the newly addressed location to the data bus. After a
propagation delay of tco (measured from the rising edge of
(dedicated thread Flag for An)
( 1 = Not Empty 0 = Empty)
(dedicated thread Flag for Am)
( 1 = Not Empty 0= Empty)
SLWR (HIGH)
FIFO ADDR
Data Out
FLAGB
FLAGA
PCLK
SLCS
SLRD
SLOE
High-Z
t
AS
Synchronous Read Cycle Timing
t
AH
t
OELZ
from addr to data
3- cycle latency
t
RDS
Figure 11. Synchronous Slave FIFO Read Mode
t
RDH
t
2 cycle latency from
CH
SLRD to FLAG
t
CYC
An
t
CL
driven:D
Data
N
t
(An)
CFLG
t
OEZ
The same sequence of events is shown for a burst read.
Note For burst mode, the SLRD# and SLOE# are asserted
during the entire duration of the read. When SLOE# is asserted,
the data bus is driven (with data from the previously addressed
FIFO). For each subsequent rising edge of PCLK, while the
SLRD# is asserted, the FIFO pointer is incremented and the next
data value is placed on the data bus.
PCLK), the new data value is present. N is the first data value
read from the FIFO. To have data on the FIFO data bus, SLOE
must also be asserted.
t
OELZ
from SLRD to data
Am
2-cycle latency
D
N+1
(An)
t
CDH
D
N
(Am)
t
CO
D
N+1
(Am) D
N+2
(Am)
t
CFLG
CYUSB301X
t
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OEZ