ISL6615 INTERSIL [Intersil Corporation], ISL6615 Datasheet - Page 5

• Manufacturer Part Number: ISL6615
• Description: High-Frequency 6A Sink Synchronous MOSFET Drivers with Protection Features
• Manufacturer: INTERSIL [Intersil Corporation]

Electrical Specifications
NOTE:
Functional Pin Description
UGATE Turn-On Propagation Delay (Note 4)
LGATE Turn-On Propagation Delay (Note 4)
UGATE Turn-Off Propagation Delay (Note 4)
LGATE Turn-Off Propagation Delay (Note 4)
LG/UG Tri-State Propagation Delay (Note 4)
OUTPUT (Note 4)
Upper Drive Source Current
Upper Drive Source Impedance
Upper Drive Sink Current
Upper Drive Sink Impedance
Lower Drive Source Current
Lower Drive Source Impedance
Lower Drive Sink Current
Lower Drive Sink Impedance
4. Limits established by characterization and are not production tested.
PACKAGE PIN #
SOIC
1
2
3
4
5
6
7
8
9
-
DFN
3, 8
10
11
1
2
4
5
6
7
9
PARAMETER
SYMBOL
PHASE
UGATE
LGATE
BOOT
PVCC
PWM
GND
VCC
PAD
PIN
N/C
Upper gate drive output. Connect to gate of high-side power N-Channel MOSFET.
Floating bootstrap supply pin for the upper gate drive. Connect the bootstrap capacitor between this pin and the
PHASE pin. The bootstrap capacitor provides the charge to turn on the upper MOSFET. See the “TIMING
DIAGRAM” on page 6 under Description for guidance in choosing the capacitor value.
No Connection. Recommend to connect pin 3 to GND and pin 8 to PVCC.
The PWM signal is the control input for the driver. The PWM signal can enter three distinct states during operation, see
the “TIMING DIAGRAM” on page 6 section under Description for further details. Connect this pin to the PWM output of
the controller.
Bias and reference ground. All signals are referenced to this node. It is also the power ground return of the driver.
Lower gate drive output. Connect to gate of the low-side power N-Channel MOSFET.
Its operating range is +6.8V to 13.2V. Place a high quality low ESR ceramic capacitor from this pin to GND.
This pin supplies power to both upper and lower gate drives. Its operating range is +4.5V to 13.2V. Place a high
quality low ESR ceramic capacitor from this pin to GND.
Connect this pin to the SOURCE of the upper MOSFET and the DRAIN of the lower MOSFET. This pin provides
a return path for the upper gate drive.
Connect this pad to the power ground plane (GND) via thermally enhanced connection.
5
Recommended Operating Conditions; Parameters with MIN and/or MAX limits are 100% tested at +25°C,
unless otherwise specified. Temperature limits established by characterization and are not production
tested. (Continued)
R
R
I
I
U_SOURCE
L_SOURCE
SYMBOL
U_SOURCE
L_SOURCE
R
R
I
I
U_SINK
t
L_SINK
t
t
t
t
U_SINK
L_SINK
PDHU
PDHL
PDLU
PDTS
PDLL
V
V
V
V
V
V
150mA Source Current
V
150mA Sink Current
V
150mA Source Current
V
150mA Sink Current
ISL6615
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
PVCC
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load, Adaptive
= 12V, 3nF Load
= 12V, 3nF Load
= 12V, 3nF Load
= 12V, 3nF Load
= 12V, 3nF Load
= 12V, 3nF Load
= 12V, 3nF Load
TEST CONDITIONS
FUNCTION
MIN
-
-
-
-
-
-
-
-
-
-
-
-
-
TYP
0.45
2.5
0.8
0.7
10
10
10
10
10
1
4
4
6
MAX
-
-
-
-
-
-
-
-
-
-
-
-
-
April 24, 2008
UNITS
FN6481.0
ns
ns
ns
ns
ns
Ω
Ω
Ω
Ω
A
A
A
A