PPC440GX-3FF533C AMCC [Applied Micro Circuits Corporation], PPC440GX-3FF533C Datasheet - Page 70

• Manufacturer Part Number: PPC440GX-3FF533C
• Description: Power PC 440GX Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

I/O Specifications—All Speeds
Notes:
1. Ethernet interface meets timing requirements as defined by IEEE 802.3 standard.
2. PCI-X timings are for asynchronous operation up to 133MHz. PCI-X input setup time requirement is 1.2ns for 133MHz and
3. The clock frequency for RMII operation is 50MHz ± 100ppm.
4. The clock frequency for SMII operation is 125MHz ± 100ppm.
5. These are DDR signals that can change on both the positive and negative clock transitions.
440GX – Power PC 440GX Embedded Processor
70
PCI-X Interface
PCIXAD00:63
PCIXC3:0[BE3:0]
PCIXParLow
PCIParHigh
PCIXFrame
PCIXINT
PCIXIRDY
PCIXTRDY
PCIXStop
PCIXDevSel
PCIXIDSel
PCIXPErr
PCIXSErr
PCIXClk
PCIXReset
PCIXReq64
PCIXAck64
PCIXCap
PCIX133Cap
PCIXM66En
PCIXReq0:5
PCIXGnt0:5
1.7ns for 66MHz. PCI timings (in parentheses) are for asynchronous operation up to 66MHz. PCI output hold time
requirement is 1ns for 66MHz and 2ns for 33MHz.
Signal
Setup Time
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
Note 2 (3)
(T
Note 2 (3
IS
na)
na
dc
na
min)
Input (ns)
Hold Time
(T
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
0.5 (0)
IH
na
dc
na
na
min)
(Sheet 1 of 7)
Valid Delay
(T
OV
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
3.8 (6)
3.8
na
na
na
na
na
dc
na
max)
Output (ns)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
0.7 (Note 2)
Hold Time
(T
OH
0.7
dc
na
na
na
na
na
na
min)
(minimum)
Output Current (mA)
I/O H
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
0.5
na
na
na
na
na
na
Revision 1.15 – August 30, 2007
(minimum)
I/O L
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
1.5
na
na
na
na
na
na
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
PCIXClk
Data Sheet
Clock
Notes
async
async
AMCC
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2
2