PPC440GRX-NPAFFFTS AMCC [Applied Micro Circuits Corporation], PPC440GRX-NPAFFFTS Datasheet - Page 11

• Manufacturer Part Number: PPC440GRX-NPAFFFTS
• Description: PowerPC 440GRx Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

Revision 1.08 – October 15, 2007
Internal Buses
The PowerPC 440GRx features four standard internal buses: two Processor Local Buses (PLBs), one On-Chip
Peripheral Buses (OPBs), and the Device Control Register Bus (DCR). The high performance, high bandwidth
cores such as the PowerPC 440 processor, the DDR SDRAM memory controller, and the PCI bridge connect to
the PLBs. OPB0 hosts lower data rate peripherals. The daisy-chained DCR provides a lower bandwidth path for
passing status and control information between the processor and the other on-chip cores.
Features include:
Security Function (optional)
The built-in security function (PPC440GRx-S only) is a cryptographic engine attached to the 128-bit PLB with built-
in DMA and interrupt controllers.
Features include:
AMCC Proprietary
Preliminary Data Sheet
• PLB4 (128-bit)
• PLB3 (64-bit)
• OPBs (OPB0)
• DCR
• Federal Information Processing Standard (FIPS) 140-2 design
• Support for an unlimited number of Security Associations (SA)
• Different SA formats for each supported protocol (IPsec/SSL/TLS/sRTP)
• Internet Protocol Security (IPSec) features
• Secure Socket Layer (SSL) and Transport Layer Security (TLS) features
• Secure Real-Time Protocol (sRTP) features
• IPsec/SSL security acceleration engine
• DES, 3DES, AES, ARC-4 encryption
• MD-5, SHA-1 hashing, HMAC encrypt-hash and hash-decrypt, and KASUMI
– 128-bit implementation of the PLB architecture
– Separate and simultaneous read and write data paths
– 36-bit address
– Simultaneous control, address, and data phases
– Four levels of pipelining
– Byte-enable capability supporting unaligned transfers
– 32- and 64-byte burst transfers
– 166MHz, maximum 5.3GB/s (simultaneous read and write)
– Processor:bus clock ratios of N:1 and N:2
– 64-bit implementation of the PLB architecture
– 32-bit address
– 166MHz (1:1 ratio with PLB4), maximum 1.3GB/s (no simultaneous read and write)
– 32-bit data path
– 32-bit address
– 83MHz
– 32-bit data path
– 10-bit address
– Full packet transforms (ESP & AH)
– Complete header and trailer processing (IPv4 and IPv6)
– Multi-mode automatic padding
– "Mutable bit" handler for AH, including IPv4 option and IPv6 extension headers
– Packet transforms
– One-pass hash-then-encrypt for SSL and TLS packet transforms for inbound packet using Stream Cipher
– Packet transforms
– ROC removal and TAG insertion
– Variable bypass offset of header length per packet
440GRx – PPC440GRx Embedded Processor
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