PPC440EP-3PBFFFCX AMCC [Applied Micro Circuits Corporation], PPC440EP-3PBFFFCX Datasheet - Page 75

• Manufacturer Part Number: PPC440EP-3PBFFFCX
• Description: Power PC 440EP Embedded Processor
• Manufacturer: AMCC [Applied Micro Circuits Corporation]

DDR SDRAM Read Operation
The following examples of timing for DDR SDRAM read operations are based on the relationship between the
incoming data and the PLB clock signal. Since the PLB clock cannot be directly observed, the delay of
MemClkOut(0) relative to the PLB clock (T
The internal Read Clock signal, like MemClkOut0, is derived from the PLB clock and can be delayed relative to the
PLB clock by programming the RDCT and RDCD fields in the SDRAM0_TR1 register. The delay can be
programmed from 0 to 1/2 cycle in steps using RDCT. Setting RDCD results in a 1/2 cycle delay plus the value set
in RDCT. The delay of Read Clock relative to the PLB clock (T
Clock delay is set to zero.
Figure 9. DDR SDRAM MemClkOut0 and Read Clock Delay
In operation, following the receipt of an address and read command from the PPC440EP, the SDRAM generates
data and the DQS signals coincident with MemClkOut0. The data is latched into the PPC440EP using a DQS
signal that is delayed 1/4 of a cycle. In order to accommodate timing variations introduced by the system designs
using this chip, the three-stage data path shown below is used to eliminate metastability and allow data sampling to
be adjusted for minimum latency. This adjustment requires programming the Read Clock delay and the selection of
Stage 1, Stage 2, or Stage 3 data for sampling at RDSP.
AMCC Proprietary
440EP – PPC440EP Embedded Processor
MemClkOut0(0)
Read Clock
PLB Clk
MD
) is provided.
T
T
T
T
MD
MD
RD
RD
T
T
RD
min = 600ps
max = 1100ps
min = 300ps
max = 740ps
MD
RD
) shown below assumes the programmable Read
Note:
min values assume best case conditions.
max values assume worst case conditions.
Revision 1.26 – April 25, 2007
Data Sheet
75