HFDOM40K3R HANBIT [Hanbit Electronics Co.,Ltd], HFDOM40K3R Datasheet - Page 12

• Manufacturer Part Number: HFDOM40K3R
• Description: 40Pin Flash Disk Module Min.16MB ~ Max.4GB, True IDE Interface Mode, 3.3V / 5.0V Operating
• Manufacturer: HANBIT [Hanbit Electronics Co.,Ltd]

HANBit
URL:www.hbe.co.kr
Rev. 2.0 (October. 2004)
4. ATA COMMAND
be mapped into the host’s I/O space because of potential conflicts on Bit 7. The bits are defined as follows:
Bit 7: this bit is in High Imoedence..
Implementation Note:
Conflicts may occur on the host data bus when this bit is provided by a Floppy Disk Controller
operating at the same addresses as the CompactFlash Storage Card. Following are some
possible solutions to this problem for the PCMCIA implementation:
1) Locate the CompactFlash Storage Card at a non-conflicting address, i.e. Secondary
address (377) or in an independently decoded Address Space when a Floppy Disk Controller
is located at the Primary addresses.
2) Do not install a Floppy and a CompactFlash Storage Card in the system at the same time.
3) Implement a socket adapter, which can be programmed to (conditionally) tri-state D7 of I/0
address 3F7h/377h when a Compact Flash Storage Card is installed and conversely to tri-state
D6-D0 of I/O address 3F7h/377h when a floppy controller is installed.
4) Do not use the CompactFlash Storage Card’s Drive Address register. This may be
accomplished by either a) If possible, program the host adapter to enable only I/O addresses
1F0h-1F7h, 3F6h (or 170h-177h, 176h) to the CompactFlash Storage Card or b) if provided
use an additional Primary / Secondary configuration in the CompactFlash Storage Card
which does not respond to accesses to I/O locations 3F7h and 377h. With either of these
implementations, the host software must not attempt to use information in the Drive Address
Register.
Bit 6 (-WTG): this bit is 0 when a write operation is in progress, otherwise, it is 1.
Bit 5 (-HS3): this bit is the negation of bit 3 in the Drive/Head register.
Bit 4 (-HS2): this bit is the negation of bit 2 in the Drive/Head register.
Bit 3 (-HS1): this bit is the negation of bit 1 in the Drive/Head register.
Bit 2 (-HS0): this bit is the negation of bit 0 in the Drive/Head register.
Bit 1 (-nDS1): this bit is 0 when drive 1 is active and selected.
Bit 0 (-nDS0): this bit is 0 when the drive 0 is active and selected.
CF-ATA Command Set
Table summarizes the CF-ATA command set with the paragraphs that follow describing the
D7
X
-WTG
D6
-HS3
D5
Card (Drive) Address Register
-HS2
D4
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-HS1
D3
-HS0
D2
HFDOM40K3R
-nDS1
D1
HANBit Electronics Co., Ltd.
-nDS0
D0