HFCT-5103D HP [Agilent(Hewlett-Packard)], HFCT-5103D Datasheet - Page 3

• Manufacturer Part Number: HFCT-5103D
• Description: SC Duplex Single Mode Transceiver
• Manufacturer: HP [Agilent(Hewlett-Packard)]

Functional Description
Receiver Section
Design
The receiver section contains an
InGaAs/InP photo detector and a
preamplifier within the receptacle,
coupled to a postamp/decision
circuit on a separate circuit board.
The postamplifier is ac coupled to
the preamplifier as illustrated in
Figure 1. The coupling capacitor
is large enough to pass the FDDI
test pattern at 125 MBd and the
SONET/SDH test pattern at
155 MBd without significant
distortion or performance penalty
If a lower signal rate, or a code
which has significantly more low
frequency content is used,
sensitivity, jitter and pulse
distortion could be degraded.
Figure 1 also shows a filter
network which limits the
bandwidth of the preamp output
signal. The filter is designed to
bandlimit the preamp output
noise and thus improve the
receiver sensitivity.
3
Figure 1 - Receiver Block Diagram
Figure 2 - p Filter Network for Noise Filtering
V
100 nF
RECEIVER
RECEPTACLE
CC
TRANS-
IMPEDANCE
PRE-
AMPLIFIER
3.3 µH
100 nF
GND
FILTERED V
+
10 µF
FILTER
CC
These components will also
reduce the sensitivity of the
receiver as the signal bit rate is
increased above 155 MBd.
Noise Immunity
The receiver includes internal
circuit components to filter
power supply noise. Under some
EMI and power supply noise
conditions, external power supply
filtering may be necessary. If
receiver sensitivity is degraded by
power supply noise, the filter
network illustrated in Figure 2
may be employed to improve
performance. The values of the
filter components are general
recommendations and may be
changed to suit a particular
system environment. Shielded
inductors are recommended.
Terminating the Outputs
The PECL Data outputs of the
receiver may be terminated with
the standard Thevenin-equivalent
50 ohm to V
Other standard PECL terminating
techniques may be used.
to DATA LINK
LIMITING
AMPLIFIER
CC
-2 V termination.
CIRCUIT
SIGNAL
DETECT
PECL
OUTPUT
BUFFER
PECL
OUTPUT
BUFFER
The two outputs of the receiver
should be terminated with
identical load circuits to avoid
unnecessary large ac current in
V
identically, the ac current is
largely nulled. The Signal Detect
output of the receiver is PECL
logic and must be loaded if it is to
be used. The Signal Detect circuit
is much slower that the data path,
so the ac noise generated by an
asymmetrical load is negligible.
Power consumption may be
reduced by using a higher than
normal load impedance for the
Signal Detect output.
Transmission line effects are not
generally a problem as the
switching rate is slow.
The Signal Detect Circuit
The Signal Detect circuit works
by sensing the peak level of the
received signal and comparing
this level to a reference.
CC
. If the outputs are loaded
DATA OUT
DATA OUT
SD