HYS64T64020HM QIMONDA [Qimonda AG], HYS64T64020HM Datasheet - Page 18

• Manufacturer Part Number: HYS64T64020HM
• Description: 214-Pin Micro-DIMM-DDR2-SDRAM Modules
• Manufacturer: QIMONDA [Qimonda AG]

16)
17)
18)
19)
20)
21) These parameters are measured from a data strobe signal ((L/U/R)DQS / DQS) crossing to its respective clock signal (CK / CK) crossing.
22) Input waveform timing is referenced from the input signal crossing at the
23) These parameters are measured from a command/address signal (CKE, CS, RAS, CAS, WE, ODT, BA0, A0, A1, etc.) transition edge to
24) Input waveform timing is referenced from the input signal crossing at the
25)
26) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
27) When the device is operated with input clock jitter, this parameter needs to be derated by the actual
28) For these parameters, the DDR2 SDRAM device is characterized and verified to support
29) DAL = WR + RU{
30)
31)
32)
Rev. 1.11, 2006-11
03062006-HT1R-Z2PY
t
which specifies when the device output is no longer driving (
t
slew rate mismatch between DQS / DQS and associated DQ in any given cycle.
t
It is used in conjunction with t
following equation;
minimum of the actual instantaneous clock low time.
t
transferred to the output; and 2) The worst case push-out of DQS on one transition followed by the worst case pull-in of DQ on the next
transition, both of which are independent of each other, due to data pin skew, output pattern effects, and pchannel to n-channel variation
of the output drivers.
t
max column. {The less half-pulse width distortion present, the larger the
Examples: 1) If the system provides
provides
The spec values are not affected by the amount of clock jitter applied (i.e.
crossing. That is, these parameters should be met whether clock jitter is present or not.
to the device under test. See
its respective clock signal (CK / CK) crossing. The spec values are not affected by the amount of clock jitter applied (i.e.
etc.), as the setup and hold are relative to the clock signal crossing that latches the command/address. That is, these parameters should
be met whether clock jitter is present or not.
to the device under test. See
t
(
driving (
calculation is consistent.
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
and
+
deratings are relative to the SDRAM input clock.) For example, if the measured jitter into a DDR2–667 SDRAM has
and
+
cycles, assuming all input clock jitter specifications are satisfied. For example, the device will support
clock cycles, if all input clock jitter specifications are met. This means: For DDR2–667 5–5–5, of which
t
Tm + 5 is valid even if (Tm + 5 - Tm) is less than 15 ns due to input clock jitter.
of the division is not already an integer, round up to the next highest integer.
DDR2–533 at
t
t
t
entire time it takes to achieve the 3 clocks of registration. Thus, after any CKE transition, CKE may not transition from its valid level during
the time period of
HZ
DQSQ
HP
QHS
QH
RPST
t
nRP
DAL.nCK
WTR
CKE.MIN
RPST
t
t
JIT.PER.MAX
JIT.DUTY.MAX
and
is the minimum of the absolute half period of the actual input clock.
=
t
t
= RU{
accounts for: 1) The pulse duration distortion of on-chip clock circuits, which represents how well the actual
is at lease two clocks (2 x
JIT.PER.MAX
JIT.DUTY.MAX
: Consists of data pin skew and output pattern effects, and p-channel to n-channel variation of the output drivers as well as output
t
end point and
), or begins driving (
HP
t
of 3 clocks means CKE must be registered on three consecutive positive clock edges. CKE must remain at the valid input level the
= WR [nCK] +
t
LZ
RPRE
–
t
HP
t
transitions occur in the same access time as valid data transitions. These parameters are referenced to a specific voltage level
t
RP
QHS
of 1420 ps into a DDR2–667 SDRAM, the DRAM provides
= 1.1 x
) by measuring the signal at two different voltages. The actual voltage measurement points are not critical as long as the
/
= 0.6 x
t
, where:
= + 93 ps, then
t
CK
CK.AVG
= + 93 ps, then
t
RP
= 3.75 ns with
t
IS
t
t
(ns) /
HP
t
RPRE
CK.AVG
+ 2 x
t
} = 5, i.e. as long as the input clock jitter specifications are met, Precharge command at Tm and Active command at
CK.AVG
t
= MIN (
t
nRP.nCK
HP
begin point are not referenced to a specific voltage level but specify when the device output is no longer driving
t
t
RPRE
CK
is the minimum of the absolute half period of the actual input clock; and
t
CK
+ 93 ps = + 2843 ps. (Caution on the MIN/MAX usage!).
+ 93 ps = + 1592 ps. (Caution on the MIN/MAX usage!).
(ns)}, where RU stands for round up. WR refers to the tWR parameter stored in the MRS. For
QHS
Figure
Figure
+
t
= WR + RU{
t
).
RPRE.MIN(DERATED)
CH.ABS
t
t
RPST.MIN(DERATED)
CK
t
Figure 2
t
IH
WR
to derive the DRAM output timing
) independent of operation frequency.
.
t
programmed to 4 clocks.
HP
,
4.
4.
t
CL.ABS
of 1315 ps into a DDR2–667 SDRAM, the DRAM provides
shows a method to calculate these points when the device is no longer driving (
t
RP
), where,
[ps] /
=
=
t
RPRE.MIN
t
RPST.MIN
t
CK.AVG
t
CH.ABS
+
[ps] }, where WR is the value programmed in the EMR.
+
t
t
t
JIT.PER.MIN
is the minimum of the actual instantaneous clock high time;
HZ
JIT.DUTY.MIN
t
DAL
), or begins driving (
18
= 4 + (15 ns / 3.75 ns) clocks = 4 + (4) clocks = 8 clocks.
t
QH
= 0.9 x
. The value to be used for
t
HP
= 0.4 x
t
V
V
QH
t
QH
IH.AC
IL.DC
is an input parameter but not an input specification parameter.
t
JIT.PER
of 1080 ps minimum.
value is; and the larger the valid data eye will be.}
t
t
CK.AVG
CK
level for a rising signal and
level for a rising signal and
t
CK.AVG
refers to the application clock period. Example: For
,
t
JIT.CC
t
LZ
– 72 ps = + 2178 ps and
) .
– 72 ps = + 928 ps and
HYS64T[32/64]0[0/2]0HM–[3S/3.7/5]–A
, etc.), as these are relative to the clock signal
t
nPARAM
Micro-DIMM DDR2 SDRAM Modules
t
= RU{
t
t
QH
QHS
QH
t
t
calculation is determined by the
of 975 ps minimum. 2) If the system
JIT.PER
JIT.DUTY
t
is the specification value under the
t
nRP
RP
t
PARAM
V
V
= 15 ns, the device will support
= RU{
IH.DC
IL.AC
of the input clock. (output
t
of the input clock. (output
t
RPRE.MAX(DERATED)
RPST.MAX(DERATED)
/
t
for a falling signal applied
for a falling signal applied
CK.AVG
t
Internet Data Sheet
t
RP
HP
/
t
t
at the input is
JIT.DUTY.MIN
JIT.PER.MIN
t
CK.AVG
}, which is in clock
t
t
t
RPST
JIT.PER
t
CL.ABS
RP
}, which is in
, if the result
), or begins
=
=
= – 72 ps
,
= – 72 ps
is the
t
t
t
RPRE.MAX
RPST.MAX
JIT.CC
,