MT58V1MV18D MICRON [Micron Technology], MT58V1MV18D Datasheet
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MT58V1MV18D
Related parts for MT58V1MV18D
MT58V1MV18D Summary of contents
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... FBGA package marking guide. Part Number Example: MT58L1MY18DT-7.5 16Mb: 1 Meg x 18, 512K x 32/36 Pipelined, DCD SyncBurst SRAM MT58L1MY18D_2.p65 – Rev 7/00 16Mb: 1 MEG x 18, 512K x 32/36 PIPELINED, DCD SYNCBURST SRAM ™ MT58L1MY18D, MT58V1MV18D, MT58L512Y32D, MT58V512V32D, MT58L512Y36D, MT58V512V36D 3.3V V I/O, Pipelined, Double-Cycle Deselect -6 -7.5 -10 NOTE: 1 ...
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ADDRESS SA0, SA1, SAs REGISTER MODE ADV# CLK ADSC# ADSP# BYTE “b” WRITE REGISTER BWb# BYTE “a” WRITE REGISTER BWa# BWE# GW# ENABLE CE# REGISTER CE2 CE2# OE# 19 ADDRESS SA0, SA1, SAs REGISTER MODE ADV# CLK ADSC# ADSP# ...
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GENERAL DESCRIPTION (continued) a burst mode input (MODE) that selects between inter- leaved and linear burst modes. The data-out (Q), en- abled by OE#, is also asynchronous. WRITE cycles can be from one to two bytes wide (x18) or from ...
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ADV# 83 ADSP# 84 ADSC# 85 ...
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TQFP PIN DESCRIPTIONS x18 x32/x36 SYMBOL 32-35, 42-50, 32-35, 42-50, 80-82, 99, 81, 82, 99, 100 100 93 93 BWa BWb# – 95 BWc# – 96 BWd BWE GW# 89 ...
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TQFP PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 84 84 ADSP ADSC MODE (LBO#) (a) 58, 59, (a) 52, 53, 62, 63, 68, 69, 56-59, 62, 63 72 12, (b) 68, 69 13, ...
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CE# BWb# NC CE2# BWE CE2 NC BWa# CLK GW ...
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FBGA PIN DESCRIPTIONS x18 x32/x36 SYMBOL 2A, 2B, 3P, 2A, 2B, 3P, 3R, 4P, 4R, 6N, 3R, 4P, 4R, 6N, 8P, 8R, 9P, 9R, 8P, 8R, 9P, 10A, 10B, 10P, 9R, 10A, 10B, 10R, 11A, 11P, ...
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FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 9A 9A ADV ADSP ADSC MODE (LB0#) (a) 10J, 10K, (a) 10J, 10K, 10L, 10M, 11D, 10L, 10M, 11J, 11E, 11F, 11G 11K, 11L, 11M (b) 1J, ...
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FBGA PIN DESCRIPTIONS (continued) x18 x32/x36 SYMBOL 3C, 3D, 3E, 3C, 3D, 3E, V 3F, 3G, 3J, 3F, 3G, 3J, 3K, 3L, 3M, 3K, 3L, 3M, 3N, 9C, 9D, 3N, 9C, 9D, 9E, 9F, 9G, 9E, 9F, 9G, 9J, 9K, ...
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INTERLEAVED BURST ADDRESS TABLE (MODE = NC OR HIGH) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 LINEAR BURST ADDRESS TABLE (MODE = LOW) FIRST ADDRESS (EXTERNAL) SECOND ADDRESS (INTERNAL) X...X00 X...X01 X...X10 X...X11 PARTIAL TRUTH TABLE FOR ...
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TRUTH TABLE (Notes 1-8) OPERATION DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down DESELECT Cycle, Power-Down SNOOZE MODE, Power-Down READ Cycle, Begin Burst READ Cycle, Begin Burst WRITE Cycle, Begin Burst READ Cycle, Begin Burst READ ...
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V , ABSOLUTE MAXIMUM DD RATINGS* Voltage on V Supply DD Relative to V ................................ -0.5V to +4.6V SS Voltage Supply DD Relative to V ................................ -0.5V to +4. (DQx) .................................... -0. ...
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V , 2.5V I/O DC ELECTRICAL CHARACTERISTICS AND OPERATING CONDITIONS DD (0ºC T +70º +3.3V ±0.165V DESCRIPTION Input High (Logic 1) Voltage Input Low (Logic 0) Voltage Input Leakage Current Output Leakage Current Output ...
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TQFP CAPACITANCE DESCRIPTION Control Input Capacitance Input/Output Capacitance (DQ) Address Capacitance Clock Capacitance FBGA CAPACITANCE DESCRIPTION Address/Control Input Capacitance Output Capacitance (Q) Clock Capacitance TQFP THERMAL RESISTANCE DESCRIPTION Thermal Resistance Test conditions follow standard test methods (Junction to Ambient) Thermal ...
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I OPERATING CONDITIONS AND MAXIMUM LIMITS DD (Note 1, unless otherwise noted)(0ºC T DESCRIPTION CONDITIONS Power Supply Device selected; All inputs V Current Cycle time IH Operating V = MAX; Outputs open DD Power Supply Device selected; ...
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AC ELECTRICAL CHARACTERISTICS AND RECOMMENDED OPERATING CONDITIONS (Notes 1, 10 unless otherwise noted) (0ºC T DESCRIPTION Clock Clock cycle time Clock frequency Clock HIGH time Clock LOW time Output Times Clock to output valid Clock to output invalid Clock to ...
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V , 3.3V I/O AC TEST CONDITIONS DD Input pulse levels ................... V .................... V Input rise and fall times ...................................... 1ns Input timing reference levels ....................... V Output reference levels ............................. V Output load .............................. See Figures 1 ...
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SNOOZE MODE SNOOZE MODE is a low-current, “power-down” mode in which the device is deselected and current is reduced The duration of SNOOZE MODE dictated by the length of time ...
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KC CLK ADSS t ADSH ADSP# ADSC ADDRESS GW#, BWE#, BWa#-BWd# t CES t CEH CE# (NOTE 2) ADV# OE# (NOTE 3) t KQLZ Q ...
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KC CLK ADSS t ADSH ADSP# t ADSS ADSC ADDRESS A1 Byte write signals are ignored for first cycle when ADSP# initiates burst. BWE#, BWa#-BWd# GW# t CES t CEH ...
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KC CLK ADSS t ADSH ADSP# ADSC ADDRESS BWE#, BWa#-BWd# (NOTE 4) t CES t CEH CE# (NOTE 2) ADV# OE High-Z t KQLZ Q ...
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IEEE 1149.1 SERIAL BOUNDARY SCAN (JTAG) The SRAM incorporates a serial boundary scan test access port (TAP). This port operates in accordance with IEEE Standard 1149.1-1990 but does not have the set of functions required for full 1149.1 compliance. These ...
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TEST DATA-OUT (TDO) The TDO output pin is used to serially clock data-out from the registers. The output is active depending upon the current state of the TAP state machine. (See Figure 5.) The output changes on the falling edge ...
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TDI, and the LSB is connected to TDO. IDENTIFICATION (ID) REGISTER The ID register is loaded with a vendor-specific, 32- bit code during the Capture-DR state when the IDCODE command is loaded in the instruction register. ...
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BYPASS When the BYPASS instruction is loaded in the in- struction register and the TAP is placed in a Shift-DR state, the bypass register is placed between TDI and TDO. The advantage of the BYPASS instruction is that it shortens ...
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TAP AC TEST CONDITIONS Input pulse levels ....................................... V Input rise and fall times ......................................... 1ns Input timing reference levels ............................. 1.25V Output reference levels ..................................... 1.25V Test load termination supply voltage ............... 1.25V TAP DC ELECTRICAL CHARACTERISTICS AND OPERATING ...
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IDENTIFICATION REGISTER DEFINITIONS INSTRUCTION FIELD 512K x 18 REVISION NUMBER xxxx (31:28) DEVICE DEPTH 00111 (27:23) DEVICE WIDTH 00011 (22:18) MICRON DEVICE ID xxxxxx (17:12) MICRON JEDEC ID 00000101100 CODE (11:1) ID Register Presence 1 Indicator (0) SCAN REGISTER SIZES ...
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FBGA BOUNDARY SCAN ORDER (x18) FBGA BIT# SIGNAL NAME DQa 9 DQa 10 DQa 11 DQa DQa 14 DQa 15 DQa 16 ...
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FBGA BOUNDARY SCAN ORDER (x32/36) FBGA BIT# SIGNAL NAME NC/DQPa 9 DQa 10 DQa 11 DQa 12 DQa 13 DQa 14 DQa 15 DQa 16 ...
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Product Family S = SRAM M = SRAM Mechanical sample X = SRAM Engineering sample Product Type B = QDR burst of 2 ™ QDR burst DDR F = SyncBurst , Pipelined, Single-Cycle Deslect ...
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PIN #1 ID 14.00 ±0.10 +0.20 16.00 -0.05 NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable mold protrusion is 0.25mm per side. 16Mb: 1 Meg x ...
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TYP Ø -.10 7.50 ±0.05 15.00 ±0.10 7.00 ±0.05 5.00 ±0.05 13.00 ±0.10 NOTE: 1. All dimensions in millimeters MAX or typical where noted. 2. Package width and length do not include mold protrusion; allowable ...
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REVISION HISTORY Changed FBGA capacitance values, Rev. 7/00, ADVANCE ............................................................................... Aug/8/ TYP 2.5 pF from 4 pF; MAX 3.5 pF from TYP 4 pF from 6 pF; MAX 5 pF from 7 pF ...