W332M72V-125SBI WEDC [White Electronic Designs Corporation], W332M72V-125SBI Datasheet

W332M72V-125SBI

Manufacturer Part Number

W332M72V-125SBI

Description

32Mx72 Synchronous DRAM

Manufacturer

WEDC [White Electronic Designs Corporation]

Datasheet

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32Mx72 Synchronous DRAM

FEATURES

BENEFITS

* This product is subject to change without notice.

Ju;y 2006

Rev. 3

High Frequency = 100, 125, 133MHz

Package:

• 208 Plastic Ball Grid Array (PBGA), 16 x 22mm

3.3V ±0.3V power supply for core and I/Os

Fully Synchronous; all signals registered on pos i tive

edge of system clock cycle

Internal pipelined operation; column address can be

changed every clock cycle

Internal banks for hiding row access/precharge

Programmable Burst length 1,2,4,8 or full page

8192 refresh cycles

Rang es

Organized as 32M x 72

Weight: W332M72V-XSBX - 2.0 grams typical

73% SPACE SAV INGS

Re duced part count

Re duced I/O count

• 23% I/O Re duc tion

Re duced trace lengths for low er par a sit ic

ca pac i tance

Suitable for hi-re li abil i ty ap pli ca tions

Lami nate in ter pos er for op ti mum TCE match

Commercial, Industrial and Military Temperature

Count

Area

I/O

22.3

White Electronic Designs

TSOP

11.9

5 x 265mm

5 x 54 pins = 270 pins

Discrete Approach

TSOP

11.9

TSOP

11.9

= 1325mm

TSOP

11.9

GENERAL DESCRIPTION

The 256MByte (2Gb) SDRAM is a high-speed CMOS,

dy nam ic ran dom-access, memory using 5 chips containing

536,870,912 bits. Each chip is internally conﬁ gured as a

quad-bank DRAM with a syn chro nous interface. Each of

the chip’s 134,217,728-bit banks is or ga nized as 8,192

rows by 1,024 columns by 16 bits.

Read and write accesses to the SDRAM are burst ori-

ented; ac cess es start at a selected location and continue

for a pro grammed number of locations in a programmed

se quence. Ac cess es be gin with the registration of an

ACTIVE com mand, which is then fol lowed by a READ or

WRITE com mand. The address bits reg is tered coincident

with the AC TIVE command are used to select the bank

and row to be accessed (BA0, BA1 select the bank; A0-

12 select the row). The address bits reg is tered co in ci dent

with the READ or WRITE com mand are used to se lect the

starting col umn lo ca tion for the burst ac cess.

The SDRAM provides for programmable READ or WRITE

burst lengths of 1, 2, 4 or 8 locations, or the full page, with

a burst terminate option. An AUTO PRECHARGE function

may be en abled to provide a self-timed row precharge that

is initiated at the end of the burst sequence.

The 2Gb SDRAM uses an internal pipelined architecture to

achieve high-speed operation. This architecture is com pat i ble

with the 2n rule of prefetch architectures, but it also allows

the column ad dress to be changed on every clock cycle to

achieve a high-speed, fully random access. Precharging

one bank while ac cess ing one of the other three banks

will hide the precharge cycles and provide seam less, high-

speed, random-access op er a tion.

The 2Gb SDRAM is designed to operate at 3.3V. An auto

refresh mode is provided, along with a power-saving,

power-down mode.

TSOP

11.9

White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com

ACTUAL SIZE

White Electronic Designs

208 Balls

352mm

W332M72V-XSBX

23%

73%

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