HYS64D16020GDL-8-A INFINEON [Infineon Technologies AG], HYS64D16020GDL-8-A Datasheet - Page 18

• Manufacturer Part Number: HYS64D16020GDL-8-A
• Description: Unbuffered DDR SDRAM SO Modules
• Manufacturer: INFINEON [Infineon Technologies AG]

7)
8) The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
9) The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
10) Fast slew rate
11) CAS Latency 1.5 operation is supported on DDR200 devices only
12)
13) For each of the terms, if not already an integer, round to the next highest integer.
14) A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
Data Sheet
t
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on
system performance (bus turnaround) degrades accordingly.
measured between
t
cycle time.
HZ
RPRES
and
is defined for CL = 1.5 operation only
t
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
1.0 V/ns , slow slew rate
V
OH(ac)
and
V
OL(ac)
.
0.5 V/ns and < 1 V/ns for command/address and CK & CK slew rate > 1.0 V/ns,
18
Unbuffered DDR SDRAM SO Modules
HYS64D16020GD(L)-[7/8]-A
t
CK
is equal to the actual system clock
t
DQSS
Electrical Characteristics
.
11042003-YIV7-VK6M
Rev. 1.02, 2004-01