HYS64D128020GU-8-A INFINEON [Infineon Technologies AG], HYS64D128020GU-8-A Datasheet - Page 14

• Manufacturer Part Number: HYS64D128020GU-8-A
• Description: 2.5 V 184-pin Unbuffered DDR-I SDRAM Modules
• Manufacturer: INFINEON [Infineon Technologies AG]

INFINEON Technologies
Electrical Characteristics & AC Timing for DDR-I components
(for reference only)
(0 C
Symbol
t
t
t
t
t
t
10. These parameters guarantee device timing, but they are not necessarily tested on each device
11. Fast slew rate >= 1.0 V/ns , slow slew rate >= 0.5 V/ns and < 1V/ns for command/address and CK & CK slew rate >1.0 V/
t
t
XSNR
XSRD
t
WTR
REFI
RFC
RCD
t
RRD
DAL
WR
1. Input slew rate >=1V/ns for DDR266 and = 1V/ns for DDR200.
2. The CK/CK input reference level (for timing reference to CK/CK) is the point at which CK and CK cross: the input reference
3. Inputs are not recognized as valid until V
4. The Output timing reference level, as measured at the timing reference point indicated in AC Characteristics (Note 3) is V
5. t
6. The maximum limit for this parameter is not a device limit. The device operates with a greater value for this parameter, but
7. The specific requirement is that DQS be valid (HIGH, LOW, or some point on a valid transition) on or before this CK edge.
8. A maximum of eight Autorefresh commands can be posted to any given DDR SDRAM device.
9. For each of the terms, if not already an integer, round to the next highest integer. tCK is equal to the actual system clock
RP
level for signals other than CK/CK, is V
to a specific voltage level, but specify when the device is no longer driving (HZ), or begins driving (LZ).
system performance (bus turnaround) degrades accordingly.
A valid transition is defined as monotonic and meeting the input slew rate specifications of the device. When no writes were
previously in progress on the bus, DQS will be transitioning from Hi-Z to logic LOW. If a previous write was in progress,
DQS could be HIGH, LOW, or transitioning from HIGH to LOW at this time, depending on t
cycle time.
ns, measured between VOH(ac) and VOL(ac)
HZ
T
A
Auto-refresh to Active/Auto-refresh
command period
Active to Read or Write delay
Precharge command period
Active bank A to Active bank B command
Write recovery time
Auto precharge write recovery
+ precharge time
Internal write to read command delay
Exit self-refresh to non-read command
Exit self-refresh to read command
Average Periodic
Refresh Interval
and t
70 C V
LZ
transitions occur in the same access time windows as valid data transitions. These parameters are not referred
DDQ
= 2.5V
Parameter
512 Mbit based
0.2V; V
REF.
DD
REF
CK/CK slew rate are >= 1.0 V/ns.
= 2.5V
stabilizes.
(twr/tck)
+ (trp/
200
Min
tck)
7.8
72
18
18
12
15
75
0.2V)
1
DDR333
14
-6
Unbuffered DDR-I SDRAM-Modules
Max
HYS64/72D64000/128020GU-7/8-A
(twr/tck)
+ (trp/
Min
tck)
200
75
20
20
15
15
75
1
DDR266A
-7
Max
7.8
DQSS
Min
200
80
20
15
20
15
80
1
2002-09-10 (rev.0.81)
DDR200
.
-8
Max
7.8
Unit
t
t
t
ns
ns
ns
ns
ns
ns
CK
CK
CK
s
Notes
1-4, 8
1-4,9
1-4
1-4
1-4
1-4
1-4
1-4
1-4
1-4
TT
.