SSD1854U ETC [List of Unclassifed Manufacturers], SSD1854U Datasheet - Page 27

• Manufacturer Part Number: SSD1854U
• Description: LCD Segment / Common Driver with Controller CMOS
• Manufacturer: ETC [List of Unclassifed Manufacturers]

Table 5 - COMMAND TABLE
Hex
00~0F
10~17
18~19
1A~1F
20~27
28~2F
30~3F
40~43
44~47
48~4B
4C~4F
50~57
58~5F
SSD1854
Series
7.13 Command Table
Bit Pattern
0000 C
0001 0C
0001 100M
0010 0R
0010 1VCVRVF
0100 00XX
L
0100 01XX
C
0100 10XX
D
0100 11XX
XXN
0101 0B
7
7
7
L
C
D
6
6
6
L
5
C
D
N
5
L
5
5
4
3
C
D
4
C
N
2
6
2
L
4
4
B
C
R
2
3
3
C
D
C
Rev 1.0
08/2002
1
N
5
1
L
0
B
C
R
3
3
1
2
2
C
C
D
0
L
4
0
N
1
2
2
0
1
L
C
D
N
0
1
1
0
C
D
0
0
Command
Set Lower
Column Address
Set Upper
Column Address
Set Master/Slave
Mode
Reserved
Set Internal
Regulator
Resistor Ratio
Set Power
Control Register
Reserved
Set Display Start
Line
Set Display
Offset
Set Multiplex
Ratio
Set N-line
Inversion
Set LCD Bias
Reserved
Description
Set the lower nibble of the column address pointer for
RAM access. The pointer is reset to 0 after reset.
Set the upper nibble of the column address pointer for
RAM access. The pointer is reset to 0 after reset.
M
M
Reserved
The internal regulator gain increases as R
increased from 000b to 111b. The factor, 1+R
given by:
R
R
R
R
R
R
R
R
(Refer to section 8.4)
VC=0: turn OFF the internal voltage booster (POR)
VC=1: turn ON the internal voltage booster
VR=0: turn OFF the internal regulator (POR)
VR=1: turn ON the internal regulator
VF=0: turn OFF the output op-amp buffer (POR)
VF=1: turn ON the output op-amp buffer
Reserved
The second command specifies the row address pointer
of the RAM data to be displayed in first row of window.
The value must be within 0 to window row number + 15.
See the RAM Mapping Table for examples.
The second command specifies the mapping of first
display line (COM0) to one of ROW0~159. COM0 is
mapped to ROW0 after reset.
The second command specifies the number of lines to
be displayed. Duties 1/16~1/160 could be selected. The
duty ratio is set to 1/160 after reset. See the Ram
Mapping Table for examples.
The second command sets the n-line inversion register
from 1 to 63 lines to reduce display crosstalk. Register
values from 00001b to 11111b are mapped to 1 line to
63 lines respectively. Value 00000b disables the N-line
inversion.
Sets the LCD bias corresponding to different mux
number.
B
000: 32mux
010: 96mux
100: 128mux
110: 160mux (POR)
Reserved
2
2
2
2
2
2
2
2
2
0
0
B
R
R
R
R
R
R
R
R
=0: Master operation mode (POR)
=1: Slave operation mode
1
1
1
1
1
1
1
1
1
B
R
R
R
R
R
R
R
R
0
0
0
0
0
0
0
0
0
:
= 000: 3.2 (POR)
= 001: 3.9
= 010: 4.6
= 011: 5.3
= 100: 6.0
= 101: 6.7
= 110: 7.4
= 111: 8.1
SOLOMON
2
22
R
2
1
/R
R
1
0
, is
is