SSD1854U ETC [List of Unclassifed Manufacturers], SSD1854U Datasheet - Page 16

• Manufacturer Part Number: SSD1854U
• Description: LCD Segment / Common Driver with Controller CMOS
• Manufacturer: ETC [List of Unclassifed Manufacturers]

11
R/W(WR)
SSD1854
Series
data bus
E(RD)
7
7.1
7.2
7.3
FUNCTIONAL BLOCK DESCRIPTIONS
Command Decoder and Command Interface
This module determines whether the input data is interpreted as data or command. Data is
directed to this module based upon the input of the
Graphic Display Data RAM (GDDRAM). If
Command and it will be decoded and written to the corresponding command register.
Reset is of the same function as Power ON Reset (POR). Once
pulse of about 1us, all internal circuitry will be back to its initial status. Refer to Command
Description section for more information.
MPU Parallel 6800-series Interface
The parallel interface consists of 8/16 data pins (D
R/ W ( WR )
(GDDRAM) or the status register.
Data RAM or Internal Command Registers depending on the status of
and
to Figure 9 of parallel timing characteristics for Parallel Interface Timing Diagram of 6800-series
microprocessors.
In order to match the operating frequency of display RAM with that of the microprocessor, some
pipeline processing is internally performed which requires the insertion of a dummy read before
the first actual display data read. This is shown in Figure 3 below.
MPU Parallel 8080-series Interface
The parallel interface consists of 8/16 data pins (D
register read is controlled by
when
Diagram of 8080-series microprocessor.
Similar to 6800-series interface, a dummy read is also required before the first actual display
data read.
CS
writ e column address
input serves as data latch signal (clock) when it is low. Whether it is display data or status
CS
CS
input serves as data latch signal (clock) when they are high and low respectively. Refer
Figure 3 – Display Data Read with the insertion of Dummy Read
Rev 1.0
08/2002
N
is low. Refer to Figure 10 of parallel timing characteristics for Parallel Interface Timing
input High indicates a read operation from the Graphic Display Data RAM
dummy read
D/ C
.
R/ W ( WR )
R/ W ( WR )
data read1
D/ C
n
input Low indicates a write operation to Display
and
is low, the input at D
0
E( RD )
-D
0
D/ C
- D
15
),
data read 2
15
R/ W ( WR )
pin. If
input indicates a write or read cycle
),
n+1
R/ W ( WR )
RES
D/ C
,
E( RD )
is high, data is written to
receives a negative reset
0
-D
,
D/ C
D/ C
15
data read 3
,
is interpreted as a
D/ C
n+2
,
input. The
E( RD )
and
SOLOMON
and
CS
E( RD )
. The
CS
.