SSD1801AV ETC [List of Unclassifed Manufacturers], SSD1801AV Datasheet - Page 10

• Manufacturer Part Number: SSD1801AV
• Description: LCD Segment / Common Driver with Controller for Character Display System
• Manufacturer: ETC [List of Unclassifed Manufacturers]

PIN DESCRIPTIONS
D/ C
When the pin is pulled low, the data at D
R/ W ( WR )
as R/W signal input. Read mode will be carried out when this pin is pulled high and write mode when low.
this pin is pulled low and the chip is selected.
DVDD & AVDD
Digital and Analog Power supply pin.
DVSS & AVSS
Ground.
E( RD )
as the enable signal, E. Read/ Write operation is initiated when this pin is pulled high and the chip is selected.
this pin is pulled low and the chip is selected.
This pin is the chip select input.
D
In 8-bit bus mode, D
D
D
D
considers first 4-bit data from MPU as the high order bits.
be fixed to high or low in serial mode
V
following relationship:
V
VL6 is the most positive LCD driving voltage. It can be supplied externally or generated by the internal regulator. It is
recommended to add a capacitor between VL6 and Vss for external regulator.
9
CS
SSD1801 Series
L6
7
3
4
L6
7
-D
-D
) in read transaction. The D
-D
This pin is Data/ Command control pin. When the pin is pulled high, the data at D
This pin is microprocessor interface input. When interfacing to a 6800-series microprocessor, this pin will be used
When interfacing to a 8080-microprocessor, this pin will be the WR input. Data write operation is initiated when
This pin must be fixed to high or low in serial mode.
This pin is microprocessor interface input. When interfacing to a 6800-series microprocessor, this pin will be used
When interfacing to a 8080-microprocessor, this pin receives the RD signal. Data read operation is initiated when
This pin must be fixed to high or low in serial mode.
These pins are the 8-bit bi-directional data bus to be connected to the microprocessor in parallel interface mode.
When serial mode is selected, D
LCD driving voltages. They can be supplied externally or generated by the internal bias divider. They have the
, V
> V
4
0
0
) by two times. The high order bits (for 8-bit mode D
) in write transaction and low order bits (8-bit mode D
L5
L5
VL5
VL4
VL3
VL2
, V
> V
L4
L4
, V
> V
L3
L3
1:4 bias
3/4 * VL6
2/4 * VL6
2/4 * VL6
1/4 * VL6
, V
7
Rev 1.1
01/2003
> V
is the MSB while D
L2
L2
> V
ss
3
-D
0
1:5 bias (default)
4/5 * VL6
3/5 * VL6
2/5 * VL6
1/5 * VL6
7
pins must be fixed to high or low in 4-bit bus mode. After resets, SSD1801
is the serial data input (SDA) and D
7
-D
0
is the LSB. In 4-bit bus mode, it is needed to transfer 4-bit data (through
0
will be transferred to the command register.
7
-D
3
-D
4
) are written before the low order bits (for 8-bit mode
0
) are read before the high order bits (8-bit mode D
6
is the serial clock input (SCK). D5-D0 must
7
-D
0
is treated as display data.
SOLOMON
7
-